See Also

A register is implemented implicitly with a Register Inference. Register Inferences in Quartus^® II VHDL support any combination of clear, preset, clock enable, and asynchronous load signals. The Quartus II software can infer memory elements from the following VHDL statements, all of which are used within a Process Statement:

• If Statements can be used to imply registers for signals and variables in the clauses of the If Statement.

• Wait Statements can be used to imply registers in a synthesized circuit. The Compiler creates flipflops for all signals and some variables that are assigned values in any process with a Wait Statement. If you use a Wait Statement, it must be listed at the beginning of the Process Statement.

During logic synthesis, the Compiler automatically inserts an instance of the register and connects it as specified in the If and/or Wait Statement(s).

You can also implement registers explicitly with Component Instantiation Statements. For more information on Component Instantiations, see Creating Hierarchical Projects.

Unlike Component Instantiations, Register Inferences are technology-independent. When registers are inferred, the Quartus II software can select them from the library you are currently using.

The following example shows methods of inferring registers that are controlled by a clock and asynchronous clear, preset, and load signals.

ENTITY reginf IS
   PORT
   (
      d, clk, clr, pre, load, data   : IN STD_LOGIC;
      q1, q2, q3, q4, q5, q6, q7     : OUT STD_LOGIC
   );
END reginf;

ARCHITECTURE maxpld OF reginf IS
BEGIN

   -- Register with active-high clock
   PROCESS
   BEGIN
       WAIT UNTIL clk = '1';         
       q1 <= d;
   END PROCESS;
   
   -- Register with active-low clock
   PROCESS
   BEGIN
       WAIT UNTIL clk = '0';          
       q2 <= d;
   END PROCESS;
   
   -- Register with active-high clock & asynchronous clear
   PROCESS (clk, clr)                      
   BEGIN
       IF clr = '1' THEN            
          q3 <= '0';
       ELSIF clk'EVENT AND clk = '1' THEN
          q3 <= d;
       END IF;
   END PROCESS;

   -- Register with active-low clock & asynchronous clear
   PROCESS (clk, clr)                     
   BEGIN
       IF clr = '0' THEN            
          q4 <= '0';
       ELSIF clk'EVENT AND clk = '0' THEN
          q4 <= d;
       END IF;
   END PROCESS;

   -- Register with active-high clock & asynchronous Preset
   PROCESS (clk, pre)                      
   BEGIN
       IF pre = '1' THEN            
          q5 <= '1';
       ELSIF clk'EVENT AND clk = '1' THEN
          q5 <= d;
       END IF;
   END PROCESS;
   
   -- Register with active-high clock & asynchronous load
   PROCESS (clk, load, data)                      
   BEGIN
       IF load = '1' THEN            
          q6 <= data;
       ELSIF clk'EVENT AND clk = '1' THEN
          q6 <= d;
       END IF;
   END PROCESS;
   
   -- Register with active-high clock & asynchronous clear & preset
   PROCESS (clk, clr, pre)                      
   BEGIN
       IF clr = '1' THEN            
          q7 <= '0';
       ELSIF pre = '1' THEN
          q7 <= '1';
       ELSIF clk'EVENT AND clk = '1' THEN
          q7 <= d;
       END IF;
   END PROCESS;

END maxpld;

In this example, all seven processes are sensitive only to changes on the control signals--that is, clk, clr, pre, and load--and to changes on the data signal data.

The first two Process Statements use Wait Statements to detect changes on the clk signal. The first process waits for a rising edge on the clk signal (that is, until clk = '1') and assigns the value d to the signal q1. The second process waits for a falling clk edge and assigns the value d to q2.

The rest of the Process Statements use an If Statement to give the asynchronous controls priority over the clk signal. This prioritization ensures that the asynchronous control signal is implemented as an asynchronous control of the D flipflop, rather than as logic connected to the D input of the flipflop.

The third and fourth Process Statements have sensitivity lists that detect changes in the clk and clr control signals and give the clr signal the higher priority. The circuit waits for an event on clk or clr, then sets q3 and q4 to '0' if clr is '1' or '0'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising or falling. When clk rises, the value of d is assigned to q3; when clk falls, the value of d is assigned to q4.

The fifth Process Statement is sensitive to clk and pre. The circuit waits for an event on clk or pre, then sets q5 to '1' if pre is '1'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising. When clk rises, the value of d is assigned to q5.

The sixth Process Statement is sensitive to clk, load, and data. The circuit waits for an event on any of these signals, then sets q6 to data if load is '1'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising. When clk rises, the value of d is assigned to q6.

The seventh Process Statement is sensitive to clk, clr, and pre. The circuit waits for an event on any of these signals, then sets q7 to '0' if clr is '1' and to '1' if pre is '1'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising. When clk rises, the value of d is assigned to q7.

For more information, see the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:

• Section 8.1: Wait Statement
• Section 8.6: If Statement
• Section 9.2: Process Statement

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