Specifies the minimum acceptable point-to-point delay, that is, the time required for a signal from an input pin or register to propagate through combinatorial logic and appear at an output pin or register. This assignment does not influence timing-driven compilation. The following table lists the legal assignment types and the path(s) affected by each assignment:
| Assignment Type/Location | Affected Path(s) |
|---|---|
|
Point-to-point assignment from register to register. Point-to-point assignment from input or bidirectional pin to register. Point-to-point assignment from register to output or bidirectional pin. |
All paths originating from the source node and feeding the destination node. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |