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To show the Timing Closure floorplan, which is an editable floorplan that shows the LogicLock^™ regions, current assignments, and fitter assignments of a project:

1. If you have not already done so, create a new project or open an existing project.

2. If necessary, create assignments in the project.

3. If you want to update the floorplan with the device, pin, logic cell (including I/O cell and embedded cell), or chip assignments from the last compilation, back-annotate assignments for the project.

4. Choose Timing Closure Floorplan (Assignments menu). More Details Shortcut