System 11 - VHDL 68HC11
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System11 is instruction set compatible with the 68HC11 WITHOUT the on chip peripherals. It includes a 1KByte 6800 SWTBUG monitor program with the stack modified to accommodate the additional Y index Register. It also contains a simple UART and timer.
Latest Revision:
Sys11-X300-5sep03.zip - Ported to the Burch ED B5-X300 Board
Software:
Swtbug11.zip - 6800 SWTBUG Monitor Modified for System11
as11.zip - Motorola 68HC11 assembler
RMCAXX.zip - Relocatable Macro Assembler and Linker by Michael L. Hasenfratz
Revision Log:
5th September 2003 - Ported to B5-X300 board
It's been brought to my attention that the Sys11-30mar03.zip does not compile / synthesize. It is due to a missing "end case" statement near line 2557 of cpu11.vhd and a missing "is" in the architecture statement at line 43. I've fixed these and rearranged the top level System11.vhd to include a Compact Flash interface. I have ported the code to the B5-X300 board, running a modified B3-SRAM module on connectors E and F, the B3-FPGA-CPU-IO module on connector D and B5-CF on connectors A & B.
The ALU ouput and condition code output is connected to connectors G & H, so I can apply timing constraints to the pins. The dual 8 bit I/O port is wired to connector C. Note that I have stripped ports C & D off the parallel I/O port, because there were not enough pins
available.
I've also inverted the clock on everything. It registers should now clock on the falling edge of the system clock. I've also made some minor changes to the divide instruction, but I have not tested if they work. The condition codes for Divide are know not to be compatible with the 68HC11. I have not tested the bit instruction .... It runs SWTBUG11 which is the monitor for the SWTPC 6800 modified to display the Y index register. SWTBUG11 is written in native 6800 code and does not exercise many of the 68HC11 instructions.30th March 2003 - Runs SWTBug11
Runs SWTBUG11 but the following instructions have been implemented but are known not to work
1. IDIV - Integer Divide
2. FDIV - Fractional Divide
3. BSET / BCLR - Bit Set & Clear
4. BRSET/BRCLR - Branch if bit Set / Clear
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