VHDL and System-on-Chip

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Abstract Goals Prerequisites Evaluation

Content ( lectures , exercises ) Exam , Curricula Feedback

Literature Newsgroups WWW links Simulators and synthesizers

Abstract

Modeling concepts for digital and analog hardware. Hardware description languages - VHDL, Verilog, HandelC. Description levels in VHDL - behavioral/functional, structural and data-flow levels. Synthesizable VHDL. Verilog and HandelC - description levels and simulation engines. Description languages for analog hardware - Spice, VHDL-AMS. Simulation and modeling in modern design tools. Hardware specification levels - system level, high level, register transfer level, and logic level. Hardware synthesis tasks at different abstraction levels. System-on-a-Chip (SoC), technological reasons. Components of SoC, bus architectures. Clock generation and distribution. Low power systems. Network on a chip. Mixed systems - analog and digital components on the same chip.

Goals

Overview and basic knowledge of VLSI design process, methods, and tools. Overview and basic knowledge of hardware description languages (VHDL, Verilog, and SystemC), their specifics, and their use both for simulation and synthesis. After the course, the students will know how to use VHDL at various design phases with the use of at least one industrial simulation and synthesis system.

Prerequisites

The basic knowledge about processor architectures, binary logic, and state machines is expected. Practical Unix/Linux knowledge is a plus.

Evaluation

The course ends with an oral exam where two questions should be answered. One of the questions covers HDLs, another covers synthesis related questions. The prerequisites for the exam are reported and passed exercises.

Content

1.  Lectures
2.  Exercises
3.  Exam -- Prerequisites - exercise passed before the examination day.

Curricula

• The need for VLSI design automation - means, possibilities, and drawbacks.
• The need for hardware description languages.
• Behavioral, dataflow, and structural styles in VHDL.
• VHDL data types, objects, and predefined operators.
• VHDL construction elements - entity, architecture, subroutines.
• Libraries and packages in VHDL. Configuration declarations.
• Signal assignment, drivers, and delays. Resolved signals.
• Parallel statements - concurrent assignments, processes, blocks, assertions.
• Entities and components - ports, binding.
• Regular structures and generate statements.
• Process statement - activation, sensitivity.
• Sequential statements. Behavioral hierarchy.
• Modeling of discrete systems. Simulation engines.
• Large project managing in VHDL.
• Synthesizable subset of VHDL. Examples.
• Verilog - base constructions, data representation, description styles.
• Behavioral, dataflow, and structural styles in Verilog.
• Time in Verilog. Simulation engines.
• Builtin details in Verilog - user primitives, nets, gates.
• SystemC - base constructions, data representation, description styles.
• Behavioral, dataflow, and structural styles in SystemC.
• Time in SystemC. Simulation engines.
• Various hardware description languages, their comparison.
• Analog extensions to hardware description languages - VHDL-AMS.
• Digital system, abstraction levels, and synthesis phases.
• Physical level synthesis.
• Logic level synthesis.
• Register transfer level synthesis.
• High-level synthesis, synthesis steps and methodology.
• Scheduling in high-level synthesis.
• Resource and time constrained scheduling. Scheduling algorithms.
• Resource allocation in high-level synthesis.
• Resource binding in high-level synthesis.
• Local timing transformations - pipelining, retiming.
• System level synthesis.
• Synthesis of high performance systems.
• Synthesis of low power systems.
• System-on-Chip - requirements for synthesis.

Literature

The list given below is not final - there exists a large number of books that can be used. In principle, it would be enough to use a book that covers both VHDL (or simulation) and synthesis related topics.

Library of TUT

• Dirk Jansen et al. (editors). The electronic design automation handbook. ch. 4,10-13 [2003]
• Michael John Sebastian Smith. Application-Specific Integrated Circuits. ch. 10,11 [1997]

• K.C. Chang. Digital systems design with VHDL and synthesis: an integrated approach. [1999]
• K.C. Chang. Digital System Design with VHDL and Synthesis. IEEE Computer Society Press [1997]
• Stefan Sjoholm and Lennart Lindh. VHDL for designers. [1997]
• David Pellerin, Douglas Taylor. VHDL made easy. [1997]
• Ben Cohen. VHDL coding styles and methodologies: [... an in-depth tutorial]. [1995]

• Ken Coffman. Real world FPGA design with Verilog. [2000]
• James M. Lee. Verilog Quickstart: a practical guide to simulation and synthesis in Verilog. [1999]
• Donald E. Thomas and Philip R. Moorby. The Verilog hardware description language. [1996]

• John F. Wakerly. Digital Design: Principles and Practices. Pearson/Prentice Hall [2006]
• M. Morris Mano. Digital Design. Prentice-Hall [2002]
• Daniel D. Gajski. Principles of Digital Design. Prentice-Hall International Inc., ch. 8 [1997]
• Douglas J. Smith HDL chip design: a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog. Doone Publications [1997]
• Ulrich Golze. VLSI chip design with the hardware description language VERILOG: an introduction based on a large RISC processor design. Springer [1996]
• David W. Knapp. Behavioral Synthesis. Digital System Design using the Synopsys Behavioral Compiler. Prentice Hall [1996]
• Giovanni De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, ch. 3,4,5,6,11 [1994]
• D.D. Gajski, F. Vahid, S. Narayan, J. Gong. Specification and Design of Embedded Systems, PTR Prentice Hall [1994]

Additional literature

• David C. Black, Jack Donovan. SystemC: From the Ground Up. Springer, 2004.
• Thorsten Grötker, Stan Liao, Grant Martin, Stuart Swan. System Design with SystemC. Springer, 2002.
• Michael Keaton, Pierre Bricaud. Reuse Methodology Manual. Kluwer Academic Publishers, 1998.
• Roland Airiau, Jean-Michel Berge, Vincent Olive. Circuit Synthesis with VHDL. Kluwer Academic Publishers, 1994.
• Daniel D. Gajski. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1993.
• Algorithmic and Knowledge Based CAD for VLSI edited by Gaynor Taylor and Gordon Russell, Peter Peregrinus Ltd., 1992.
• The Synthesis Approach to Digital System Design. Edited by Petra Michel, Ulrich Lauter, Peter Duzy, Kluwer Academic Publishers, 1992.
• Logic and Architecture Synthesis. edited by Petra Michel, Gabrielle Saucier, 1991, North-Holland.
• R.Lipsett, C.F.Schaeffer, C. Ussery. VHDL: Hardware Description and Design. Kluwer Academic Publishers, 1990.

Newsgroups

• comp.cad.synthesis
• comp.lang.vhdl         (see also FAQ)
• comp.lang.verilog

WWW links

There exist hundreds of links. For the beginning...

• Peter J. Ashenden The Student's Guide to VHDL & The Designer's Guide to VHDL
• ASIC Design with VHDL
• Robert Reese Course notes on Logic Design Course with VHDL & Course notes on Modeling with VHDL
• VHDL-Online

• Project Veripage
• Alternate Verilog FAQ
• Verilog Resources

• SystemC Community

• Educational Java Applet Service
• Computer Arithmetic Algorithm Simulator

Simulators & synthesizers

Mostly freeware

• WebFITTER - online simulation and synthesis from Xilinx.
• WebPACK - simulation and synthesis and synthesis tool from Xilinx (MS Windows & Linux), uses ModelSim's simulator.
• Alliance - Pierre and Marie Curie University LIP6 laboratory CAD tool set (freeware).
• Blue Pacific Computing, Inc. simulators - VHDL, Verilog and SystemC (Windows, Linux & Solaris; limited amount of code - <50Kb of source).
• VHDL Simili - Symphony EDA simulator (free, limited possibilities).
• Accolade Peak-HDL simulator (MS Windows, a book with CD: D. Pellerin "VHDL Made Easy!").
• Active-VHDL Simulation design environment (30-day full trial license).
• Veribest VHDL simulator (30-day full trial license, up to 2000 lines/gets after that).
• Model Technology ModelSim (limited size of the design, enough for course projects, Internet connection needed to obtain free license).
• SystemC_Win - SystemC simulator for Windows (free for non-commercial use).
• Green Mountain's compiler/simulator (free demo version, limited number of lines and VHDL'93 functionality).
• Verilog simulator (Linux)
• UDL/I simulator (Unix/Linux)

Last modified 2008.12.15