Computer Aids for VLSI Design
Steven M. Rubin
Copyright © 1994
Appendix F: References for the Entire Book
-
Abramovici, M.; Levendel, Y.H.; and Menon, P.R., "A Logic Simulation Machine,"
Proceedings 9th Symposium on Computer Architecture,
SIGArch Newsletter, 10:3, 148-157, April 1982.
[6]
-
Ackland, Bryan; Dickenson, Alex; Ensor, Robert; Gabbe, John; Kollaritsch, Paul;
London, Tom; Poirier, Charles; Subrahmanyam, P.; and Watanabe, Hiroyuki,
"CADRE-A System of Cooperating VLSI Design Experts," Proceedings IEEE
International Conference on Computer Design, 99-104, October 1985.
[1, 4]
-
Ackland, Bryan and Weste, Neil, "Realtime Animation Playback on a
Frame Store Display System," Computer Graphics, 14:3, 182-188,
August 1980.
[9]
-
Ackland, Bryan and Weste, Neil, "An Automatic Assembly Tool for
Virtual Grid Symbolic Layout," VLSI '83 (Anceau and Aas, eds),
North Holland, Amsterdam, 457-466, August 1983.
[4]
-
Adobe Systems Incorporated, PostScript Language Tutorial and Cookbook,
Addison-Wesley, Reading, Massachusetts, 1985.
[9]
-
ANSI, Programmer's Hierarchical Interactive Graphics Standard (PHIGS),
American National Standards Institute X3H3/84-40, February 1984.
[9]
-
Applicon, Bravo3 User's Guide, Applicon Incorporated, Ann Arbor, Michigan,
1986.
[10]
-
Applicon, IAGL User's Guide, Applicon Incorporated, Burlington,
Massachusetts, June 1983.
[8]
-
Arnold, John E., "The Knowledge-Based Test Assistant's Wave/Signal Editor:
An Interface for the Management of Timing Constraints," Proceedings 2nd
Conference on Artificial Intelligence Applications, 130-136, December 1985.
[3, 8]
-
Arnold, Michael H. and Ousterhout, John K., "Lyra: A New Approach to
Geometric Layout Rule Checking," Proceedings 19th Design Automation
Conference, 530-536, June 1982.
[5]
-
Atkinson, William D.; Bond, Karen E.; Tribble, Guy L.; and Wilson, Kent R.,
"Computing with Feeling," Computers and Graphics, 2:2, 97-103, 1977.
[9]
-
Atwood, Thomas M., "An Object-Oriented DBMS for Engineering Design Support
Applications," Proceedings Compint Conference, Montreal, 299-307, September
1985.
[3]
-
Ayres, Ronald F., VLSI Silicon Compilation and the Art of Automatic
Microchip Design, Prentice-Hall, Englewood Cliffs, New Jersey, 1983.
[4]
-
Baird, Henry S., "Fast Algorithms for LSI Artwork Analysis", Proceedings 14th
Design Automation Conference, 303-311, June 1977.
[5]
-
Baird, H. S. and Cho, Y. E., "An Artwork Design Verification System,"
Proceedings 12th Design Automation Conference, 414-420, June 1975.
[5]
-
Baker, Clark M. and Terman, Chris, "Tools for Verifying Integrated Circuit
Designs," Lambda, 1:3, 22-30, 4th Quarter 1980.
[4, 5, 11]
-
Balraj, T. S. and Foster, M. J., "Miss Manners: A Specialized Silicon Compiler
for Synchronizers," Proceedings 4th MIT Conference on Advanced Research in
VLSI (Leiserson, ed), 3-20, April 1986.
[4]
-
Baray, Mehmet B. and Su, Stephen Y. H., "A Digital System Modeling Philosophy
and Design Language," Proceedings 8th Design Automation Workshop, 1-22,
June 1971.
[2]
-
Barrow, Harry G., "VERIFY: A Program for Proving Correctness of Digital
Hardware Designs," Artificial Intelligence, 24:1-3, 437-491, December
1984.
[5]
-
Barsky, Brian A. and Beatty, John C., "Local Control of Bias and
Tension in Beta-splines," Computer Graphics, 17:3, 193-218, July 1983.
[9]
-
Barton, E. E. and Buchanan, I., "The Polygon Package," Computer Aided
Design, 12:1, 3-11, January 1980.
[3]
-
Batali, J. and Hartheimer, A., "The Design Procedure Language Manual,"
AI Memo 598, Massachusetts Institute of Technology, 1980.
[3, 8, 11]
-
Baumgart, Bruce Guenther, Geometric Modeling for Computer Vision,
PhD dissertation, Stanford University, August 1974.
[3]
-
Bell, C. Gordon; Grason, John; and Newell, Allen, Designing Computers and
Digital Systems Using PDP 16 Register Transfer Modules, Digital Press,
Maynard, Massachusetts, 1972.
[2]
-
Bell, C. Gordon and Newell, Allen, Computer Structures: Readings and
Examples, McGraw-Hill, New York, 1971.
[2]
-
Bell, J. L. and Slomson, A. B., Models and Ultraproducts: An Introduction,
North-Holland and American Elsevier, New York, 1971.
[2]
-
Bentley, Jon Louis; Haken, Dorthea; and Hon, Robert W., "Fast Geometric
Algorithms for VLSI Tasks," Proceedings 20th IEEE Compcon, 88-92,
February 1980.
[5]
-
Beresford, Roderic, "Comparing Gate Arrays and Standard-Cell ICs,"
VLSI Design, IV:8, 30-36, December 1983.
[4]
-
Bezier, P, Numerical Control-Mathematics and Applications,
(A. R. Forest, trans), Wiley, London, 1972.
[9]
-
Blank, Tom, "A Survey of Hardware Accelerators Used in Computer-Aided
Design," IEEE Design and Test, 1:3, 21-39, August 1984.
[4]
-
Bobrow, Daniel G.; Burchfiel, Jerry D.; Murphy, Daniel L.; and Tomlinson, Raymond
S., "TENEX: A Paged Time Sharing system for the PDP-10," CACM, 15:3
135-143, March 1972.
[10]
-
Borning, Alan, "ThingLab-A Constraint-Oriented Simulation Laboratory,"
PhD dissertation, Stanford University, July 1979.
[3, 8]
-
Borriello, Gaetano, "WAVES: A Digital Waveform Editor for the Design,
Documentation, and Specification of Interfaces," unpublished document.
[3, 8]
-
Borriello, Gaetano; Katz, Randy H.; Bell, Alan G.; and Conway, Lynn,
"VLSI System Design by the Numbers," IEEE Spectrum, 22:2, 44-50,
February 1985.
[7]
-
Breshenham, J. E., "Algorithm for Computer Control of Digital Plotter,"
IBM Systems Journal, 4:1, 25-30, 1965.
[9]
-
Breshenham, J. E., "A Linear Algorithm for Incremental Digital Display
of Circular Arcs," CACM, 20:2, 100-106, February 1977.
[9]
-
Breuer, Melvin A., "A Class of Min-Cut Placement Algorithms," Proceedings 14th
Design Automation Conference, 284-290, June 1977.
[4]
-
Brown, Harold; Tong, Christofer; and Foyster, Gordon, "Palladio: An
Exploratory Environment for Circuit Design," IEEE Computer, 16:12,
41-56, December 1983.
[1, 3, 8]
-
Bryant, Randal Everitt, A Switch-Level Simulation Model for Integrated
Logic Circuits, PhD dissertation, Massachusetts Institute of Technology
Laboratory for Computer Science, report MIT/LCS/TR-259, March 1981.
[6, 11]
-
Bryant, Randal, "Preface", Proceedings 3rd Caltech Conference on VLSI
(Bryant ed), Computer Science Press, v-viii, March 1983.
[3]
-
Buric, Misha R. and Matheson, Thomas G., "Silicon Compilation Environments,"
Proceedings Custom Integrated Circuits Conference, 208-212, May 1985.
[4, 8]
-
Burstein, Michael; Hong, Se June; and Pelavin, Richard, "Hierarchical
VLSI Layout: Simultaneous Placement and Wiring of Gate Arrays,"
VLSI '83 (Anceau and Aas, eds), North Holland, Amsterdam,
45-60, August 1983.
[4]
-
CAE Corporation, CAE 2000 Command Language User's Manual, August 1984.
[8]
-
Calma Corporation, GDS II Stream Format, July 1984.
[7]
-
Calma, GPL II Programmers Reference Manual, GE Calma Company,
February 1981.
[8]
-
Card, Stuart K.; Moran, Thomas P.; and Newell, Allen, The Psychology of
Human-Computer Interaction, Lawrence Erlbaum, Hillsdale, New Jersey, 1983.
[10]
-
Catmull, Edwin, "A Hidden Surface Algorithm with Anti-Aliasing,"
Computer Graphics, 12:3, 6-11, August 1978.
[9]
-
Chao, Shiu-Ping; Huang, Yen-Son; and Yam, Lap Man, "A Hierarchical Approach
for Layout Versus Circuit Consistency Check," Proceedings 17th Design Automation
Conference, 270-276, June 1980.
[5]
-
Chawla, Basant R.; Gummel, Hermann K.; and Kozak, Paul, "MOTIS-An MOS Timing
Simulator," IEEE Transactions on Circuits and Systems, CAS-22:12, 901-910,
December 1975.
[6]
-
Chen, C.F.; Lo, C-Y.; Nham, H.N.; and Subramaniam, Prasad,
"The Second Generation MOTIS Mixed-Mode Simulator," Proceedings 21st Design
Automation Conference, 10-17, June 1984.
[6]
-
Cheng, Chung-Kuan and Kuh, Ernest S., "Module Placement Based on Resistive
Network Optimization," IEEE Transactions on CAD, 3:3, 218-225,
July 1984
[4]
-
Cherry, James; Shrobe, Howard; Mayle, Neil; Baker, Clark; Minsky, Henry;
Reti, Kalman; and Weste, Neil, "NS: An Integrated Symbolic Design System,"
VLSI '85, (Horbst, ed), 325-334, August 1985.
[8]
-
Chiba, Toshiaki; Takashima, Makoto; and Mitsuhashi, Takashi, "A Mask Artwork
Analysis System for Bipolar Integrated Circuits," Proceedings 21st IEEE Compcon,
175-183, September 1981.
[5]
-
CMC, Guide to the Integrated Circuit Implementation Services of the Canadian
Microelectronics Corporation, version 2:0, Kingston Ontario, January 1986.
[7]
-
Clark, G. C. and Zippel, R. E., "Schema: An Architecture for Knowledge
Based CAD," ICCAD '85, 50-52, November 1985.
[3]
-
Clarke, Edmund and Feng, Yulin, "Escher-A Geometrical Layout System for
Recursively Defined Circuits," Proceedings 23rd Design Automation Conference,
650-653, June 1986.
[8]
-
Computervision, CADDS II/VLSI Integrated Circuit Programming Language User's
Guide, Computervision Corporation Document 001-00045, Bedford, Massachusetts,
April 1986.
[8]
-
Conway, Lynn; Bell, Alan; and Newell, Martin E., "MPC79: The
Demonstration-Operation of a Prototype Remote-Entry Fast-Turnaround VLSI
Implementation System," Proceedings MIT Conference on Advanced Research in
Integrated Circuits, January 1980 (also reprinted in Lambda, 1:2, 10-19,
2nd Quarter 1980).
[7]
-
Crawford, B. J., "Design Rules Checking for Integrated Circuits Using
Graphical Operators," Computer Graphics, 9:1, 168-176, 1975.
[5]
-
Curry, James E., "A Tablet Input Facility for an Interactive Graphics System,"
Proceedings IJCAI '69, 33-40, May 1969.
[10]
-
Davis, A. L. and Drongowski, P. J., "Dataflow Computers: A Tutorial and
Survey," University of Utah UUCS-80-109, July 1980.
[2]
-
Davis, Tom, and Clark, Jim, "SILT: A VLSI Design Language," Stanford University
Computer Systems Laboratory Technical Report 226, October 1982.
[8]
-
Deas, Alex R. and Nixon, Ian M., "Chromatic Idioms for Automated VLSI
Floorplanning," VLSI '85, (Horbst, ed), 61-70, August 1985.
[4]
-
De Man, Hugo J.; Bolsens, I.; Meersch, Erik Vanden; and Cleynenbreugel, Johan
Van, "DIALOG: An Expert Debugging System for MOSVLSI Design," IEEE
Transactions on CAD, 4:3, 303-311, July 1985.
[5]
-
Denneau, Monty M., "The Yorktown Simulation Engine," Proceedings 19th Design
Automation Conference, 55-59, June 1982.
[6]
-
Dennis, J. B., Fosseen, J. B., and Linderman, J. P., "Data Flow Schemas,"
Proceedings International Symposium on Theoretical Programming, 187-216,
1972.
[2]
-
Denyer, Peter B.; Murray, Alan F.; and Renshaw, David, "FIRST-Prospect
and Retrospect," VLSI Signal Processing, IEEE press, New York, 252-263,
1984.
[4]
-
Deutsch, David N., "A 'Dogleg' Channel Router," Proceedings 13th Design
Automation Conference, 425-433, June 1976.
[4]
-
Deutsch, L. P. and Bobrow, D. G., "An Efficient Incremental Automatic
Garbage Collector," CACM, 19:9, 522-526, September 1976.
[3]
-
Digital, PDP10 Timesharing Handbook, Digital Press, Maynard, Massachusetts,
1970.
[10]
-
Do, James and Dawson, William M., "Spacer II: A Well-Behaved IC Layout
Compactor," VLSI '85, (Horbst, ed), 283-291, August 1985.
[4]
-
Dobes, Ivan and Byrd, Ron, "The Automatic Recognition of Silicon Gate
Transistor Geometries: An LSI Design Aid Program," Proceedings 13th Design
Automation Conference, 327-335, June 1976.
[5]
-
Department of Defense, "Graphic Symbols for Logic Diagrams," MIL-STD-806B,
Washington, D.C., February 1962.
[2]
-
Doreau, Michel T. and Koziol, Piotr, "TWIGY: A Topological Algorithm Based
Routing System," Proceedings 18th Design Automation Conference, 746-755,
June 1981.
[4]
-
Dunlop, A. E., "SLIM-The Translation of Symbolic Layouts into Mask Data,"
Proceedings 17th Design Automation Conference, 595-602, June 1980.
[4]
-
Ebeling, Carl and Zajicek, Ofer, "Validating VLSI Circuit Layout by
Wirelist Comparison," ICCAD '83, 172-173, September 1983.
[1, 5]
-
Electronic Design Interface Format Steering Committee,
EDIF-Electronic Design Interchange Format Version 1 0 0,
Texas Instruments, Dallas, Texas, 1985.
[7, 11]
-
Entenman, George and Daniel, Stephen W., "A Fully Automatic Hierarchical
Compactor," Proceedings 22nd Design Automation Conference, 69-75, June 1985.
[4]
-
Eustace, R. Alan and Mukhopadhyay, Amar, "A Deterministic Finite Automaton
Approach to Design Rule Checking For VLSI," Proceedings 19th Design
Automation Conference, 712-717, June 1982.
[5]
-
Factron, "CADDIF Version 2.0 Engineering Specifications," Schlumberger
Factron, October 1985.
[7]
-
Fairbairn, D. G. and Rowson, J. A., "ICARUS: An Interactive Integrated
Circuit Layout Program," Proceedings 15th Design Automation
Conference, 188-192, June 1978.
[10]
-
Feller, A., "Automatic Layout of Low-Cost Quick-Turnaround Random-Logic
Custom LSI Devices", Proceedings 13th Design Automation Conference,
79-85, June 1976.
[2]
-
Fishburn, J. P. and Dunlop, A. E., "TILOS: A Posynomial Programming Approach
to Transistor Sizing," ICCAD '85, 326-328, November 1985.
[5]
-
Foley, J. D. and Van Dam, A., Fundamentals of Interactive
Computer Graphics, Addison-Wesley, Reading, Massachusetts, 1982.
[9]
-
Freeman, William J. III and Freund, Vincent J. Jr., "A History of
Semicustom Design at IBM," VLSI Systems Design, Semicustom Design
Guide, 14-22, Summer 1986.
[4]
-
Frey, Ernest J., "ESIM: A Functional Level Simulation Tool,"
ICCAD '84, 48-50, November 1984.
[6]
-
Fuchs, Henry; Poulton, John; Paeth, Alan; and Bell, Alan, "Developing
Pixel-Planes, A Smart Memory-Based Raster Graphics System," Proceedings MIT
Conference on Advanced Research in VLSI (Penfield, ed), 137-146, January 1982.
[9]
-
Gajski, Daniel D., "ARSENIC Silicon Compiler," Proceedings International
Symposium on Circuits and Systems, 399-402, June 1985.
[4]
-
Garey, Michael R. and Johnson, David S., Computers and Intractability,
A Guide to the Theory of NP-Completeness, W.H. Freeman, San Francisco,
1979.
[4]
-
Gerber Corporation, "Gerber Format," Gerber Scientific Instrument Company
document number 40101-S00-066A, July 1983.
[7]
-
German, Steven M. and Wang, Yu, "Formal Verification of Parameterized Hardware
Designs," Proceedings IEEE International Conference on Computer Design,
549-552, October 1985.
[5]
-
Gibson, Dave and Nance, Scott, "SLIC-Symbolic Layout of Integrated
Circuits," Proceedings 13th Design Automation Conference, 434-440, June 1976.
[1, 2]
-
Glasser, Lance A. and Dobberpuhl, Daniel W., The Design and Analysis of
VLSI Circuits, Addison-Wesley, Reading, Massachusetts, 1985.
[2, 6]
-
Goates, Gary B.; Harris, Thomas R.; Oettel, Richard E.; and Waldron, Harvey
M. III, "Storage/Logic Array Design: Reducing Theory to Practice,"
VLSI Design, III:4, 56-62, 1982.
[4]
-
Gordon, M., "A Very Simple Model of Sequential Behaviour of nMOS,"
VLSI '81 (Gray, ed), Academic Press, London, 85-94, August 1981.
[5]
-
Gordon, Mike, "HOL-A Machine Oriented Formulation of Higher Order Logic,"
University of Cambridge Computer Laboratory, technical report 68, July 1985.
[5]
-
Gosling, James, Algebraic Constraints, PhD dissertation, Carnegie-Mellon
University, CMU-CS-83-132, May 1983.
[3, 8]
-
Gosling, James, personal communications.
[10]
-
GPSC, "Status Report of the Graphic Standards Planning Committee,"
Computer Graphics, 13:3, August 1979.
[9]
-
Griswold, Thomas W., "Portable Design Rules for Bulk CMOS," VLSI Design,
III:5, 62-67, September/October 1982.
[11]
-
Gross, A. G.; Raamot, J.; and Watkins, S. B., "Computer Systems for
Pattern Generator Control," Bell Systems Technical Journal, 49:9,
2011-2029, November 1970.
[7]
-
Grundmann, John W., "Event-Driven MOS Timing Simulator,"
ICCAD '83, 141-142, September 1983.
[6]
-
Guttman, Antonin, "R-Trees: A Dynamic Index Structure for Spatial Searching,"
ACM SIGMOD, 14:2, 47-57, June 1984.
[3, 11]
-
Haber, Ralph Norman, "How We Remember What We See," Scientific American,
222:5, 104-112, May 1970.
[10]
-
Hachtel, G. D.; Newton, A. R.; and Sangiovanni-Vincentelli, A. L., "Techniques
for Programmable Logic Array Folding," Proceedings 19th Design Automation
Conference, 147-155, June 1982.
[4]
-
Hamachi, Gordon T. and Ousterhout, John K., "A Switchbox Router with Obstacle
Avoidance," Proceedings 21st Design Automation Conference, 173-179,
June 1984.
[4]
-
Harrison, D. S.; Moore, P.; Spickelmier, R. L.; and Newton, A. R., "Data Management
and Graphics Editing in the Berkeley Design Environment," 1986 IEEE International
Conference on Computer-Aided Design, 24-27, 1986.
[11]
-
Harrison, Richard A. and Olson, Daniel J., "Race Analysis of Digital
Systems Without Logic Simulation," Proceedings 8th Design Automation
Workshop, 82-94, June 1971.
[5]
-
Heller, W. R., "An Algorithm for Chip Planning," Caltech Silicon Structures
Project file #2806, 1979.
[4]
-
Heller, William R.; Sorkin, G.; Maling, Klim, "The Planar Package Planner
for System Designers," Proceedings 19th Design Automation Conference,
253-260, June 1982.
[4]
-
Hellestrand, G. R.; Tan, C. H.; Yong, F. N.; and Forster, R. L., "Australian
Multi-Project Chip Activities, 1982-1986", Joint Microelectronics Research
Centre, University of New South Wales, October 1986.
[7]
-
Henderson, Peter, "Functional Geometry," Proceedings ACM Symposium on LISP and
Functional Programming, 179-187, August 1982.
[8]
-
Hennion, B. and Senn, P., "A New Algorithm for Third Generation Circuit
Simulators: The One-Step Relaxation Method," Proceedings 22nd Design Automation
Conference, 137-143, June 1985.
[6]
-
HHB, CADAT User's Manual, Revision 5.0, HHB-Softron, Mahwah, New Jersey,
June 1985.
[11]
-
Hightower, D. W., "A Solution to Line-Routing Problems in the Continuous
Plane," Proceedings 6th Design Automation Workshop, 1-24, June 1969.
[4]
-
Holt, Dan and Sapiro, Steve, "BOLT-A Block Oriented Design Specification
Language," Proceedings 18th Design Automation Conference, 276-279, June 1981.
[8]
-
Hon, Robert W., The Hierarchical Analysis of VLSI Designs, PhD
dissertation, Carnegie-Mellon University Computer Science Department,
CMU-CS-83-170, December 1983.
[5]
-
Hon, Robert W. and Sequin, Carlo H., "A Guide to LSI Implementation," 2nd
Edition, Xerox Palo Alto Research Center technical memo SSL-79-7,
January 1980.
[4, 7, 11]
-
Horowitz, Mark, "Timing Models for MOS Pass Networks," Proceedings International
Symposium on Circuits and Systems, 198-201, May 1983.
[5]
-
Hsueh, Min-Yu and Pederson, Donald O., "Computer-Aided Layout of LSI
Circuit Building-Blocks," Proceedings International Symposium on Circuits
and Systems, 474-477, July 1979.
[4, 8]
-
IBM, Advanced Statistical Analysis Program (ASTAP), IBM Corporation
Data Products Division, Publication SH20-1118-0, White Plains, New York.
[6]
-
Insinga, Aron K., "Behavioral Modeling in a Structural Logic Simulator,"
ICCAD '84, 42-44, November 1984.
[6]
-
Jain, Sunil K. and Agrawal, Vishwani D., "Modeling and Test Generation
Algorithms for MOS Circuits," IEEE Transactions on Computers, C-34:5,
426-433, May 1985.
[6]
-
Jarvis, J. F.; Judice, C. N.; and Ninke, W. H., "A Survey of Techniques
for the Image Display of Continuous Tone Pictures on Bilevel Displays,"
Computer Graphics and Image Processing, 5:1, 13-40, March 1976.
[9]
-
Johannsen, D. L., "Bristle Blocks: A Silicon Compiler," Proceedings 16th
Design Automation Conference, 310-313, June 1979.
[4]
-
Johnson, Dean P. and Lipman, Jim, "IC Packaging: An Introduction For
the VLSI Designer," VLSI Systems Design, VII:6, 108-116, June 1986.
[7]
-
Johnson, Stephen C., "Hierarchical Design Validation Based on Rectangles,"
Proceedings MIT Conference on Advanced Research in VLSI (Penfield, ed), 97-100,
January 1982.
[5, 8, 11]
-
Jouppi, Norman P., "TV: An nMOS Timing Analyzer," Proceedings 3rd
Caltech Conference on VLSI (Bryant, ed), Computer Science Press, 71-85,
March 1983.
[5]
-
Kahrs, Mark, "Silicon compilation of a very high level signal processing
specification language," VLSI Signal Processing, IEEE press, New York,
228-238, 1984.
[4]
-
Kaplan, David, "A 'Non-Restrictive' Artwork Verification Program for
Printed Circuit Boards," Proceedings 19th Design Automation Conference,
551-558, June 1982.
[5]
-
Karplus, Kevin, "Exclusion Constraints, a new application of Graph
Algorithms to VLSI Design," Proceedings 4th MIT Conference on Advanced
Research in VLSI (Leiserson, ed), 123-139, April 1986.
[3, 5]
-
Kedem, Gershon, "The Quad-CIF Tree: A Data Structure for Hierarchical On-Line
Algorithms," Proceedings 19th Design Automation Conference, 352-357, June 1982.
[3]
-
Keller, John, Power and Ground Requirements for a High Speed 32 Bit Computer
Chip Set, Masters thesis, University of California at Berkeley,
UCB/CSD 86/253, August 1985.
[4]
-
Kernighan, Brian W. and Ritchie, Dennis M., The C Programming Language,
Prentice-Hall, Englewood Cliffs, New Jersey, 1978.
[11]
-
Kernighan, B. W.; Schweikert, D. G.; and Persky, G., "An Optimum Channel-Routing
Algorithm for Polycell Layouts of Integrated Circuits," Proceedings 10th
Design Automation Workshop, 50-59, June 1973.
[4]
-
Ketonen, Jussi and Weening, Joseph S., "EKL-An Interactive Proof Checker
User's Reference Manual," Stanford University Department of Computer Science,
report STAN-CS-84-1006, June 1984.
[5]
-
Kim, Jin H.; McDermott, John; and Siewiorek, Daniel P., "Exploiting Domain
Knowledge in IC Cell Layout," IEEE Design and Test, 1:3, 52-64, 1984.
[4]
-
Kingsley, C., Earl: An Integrated Circuit Design Language, Masters
Thesis, California Institute of Technology, June 1982.
[8, 11]
-
Kirkpatrick, S.; Gelatt, C. D. Jr.; and Vecchi, M. P., "Optimization
by Simulated Annealing," Science, 220:4598, 671-680, May 1983.
[4]
-
Kollaritsch, P. W. and Weste, N. H. E., "A Rule-Based Symbolic Layout Expert,"
VLSI Design, V:8, 62-66, August 1984.
[4]
-
Koppelman, George M. and Wesley, Michael A., "OYSTER: A Study of Integrated
Circuits as Three-Dimensional Structures," IBM Journal of Research and
Development, 27:2, 149-163, March 1983.
[1]
-
Kors, J. L. and Israel, M., "An Interactive Electrical Graph Extractor,"
Proceedings 21st Design Automation Conference, 624-628, June 1984.
[5]
-
Kostiuk, A. R., "QUISC: An Interactive Silicon Compiler,"
M.Sc. Thesis, Queen's University at Kingston, Department of Electrical Engineering, 1987.
[11]
-
Kowalski, T. J. and Thomas, D. E., "The VLSI Design Automation Assistant:
Prototype System," Proceedings 20th Design Automation Conference, 479-483,
June 1983.
[4]
-
Kozminski, Krzysztof and Kinnen, Edwin, "An Algorithm for Finding a Rectangular
Dual of a Planar Graph for Use in Area Planning for VLSI Integrated Circuits,"
Proceedings 21st Design Automation Conference, 655-656, June 1984.
[4]
-
Knuth, Donald E., The Art of Computer Programming, Volume 1/Fundamental
Algorithms, Addison-Wesley, Reading, Massachusetts, 1969.
[3]
-
Knuth, Donald E., TEX and METAFONT-New Directions in Typesetting,
Digital Press, Bedford, Massachusetts, 1979.
[9]
-
Kroeker, Wallace I., Integrated Environmental Support for Silicon
Compilation of Digital Filters, Masters Thesis, University of Calgary
Computer Science Department, March 1986.
[11]
-
Lanfri, Ann R., "PHLED45: An Enhanced Version of Caesar Supporting 45 degree
Geometries," Proceedings 21st Design Automation Conference, 558-564,
June 1984.
[3]
-
Lansky, A. L. and Owicki, S. S., "GEM: A Tool for Concurrency Specification
and Verification," Proceedings 2nd Annual ACM Symposium on Principles of
Distributed Computing, 198-212, August 1983.
[11]
-
Lathrop, Richard H. and Kirk, Robert S., "An Extensible Object-Oriented
Mixed-Mode Functional Simulation System," Proceedings 22nd Design Automation
Conference, 630-636, June 1985.
[6]
-
Lauther, Ulrich, "Channel Routing in a General Cell Environment," VLSI '85,
(Horbst, ed), 393-403, August 1985.
[4]
-
Lee, C. Y., "An Algorithm for Path Connections and Its Applications,"
IRE Transactions on Electronic Computers, EC-10, 346-365,
September 1961.
[4]
-
Leinwand, Sany M., "Integrated Design Environment," unpublished manuscript,
April 1984.
[3]
-
Liblong, Breen M., SHIFT-A Structured Hierarchical Intermediate Form for
VLSI Design Tools, Masters Thesis, University of Calgary Department of
Computer Science, September 1984.
[7]
-
Lightner, M.R.; Moceyunas, P.H.; Mueller, H.P.; Vellandi, B.L.; and
Vellandi, H.P., "CSIM: The Evolution of a Behavioral Level Simulator from
a Functional Simulator: Implementation Issues and Performance Measurements,"
ICCAD '85, 350-352, November 1985.
[6]
-
Lin, Tzu-Mu and Mead, Carver A., "Signal Delay in General RC Networks
with Application to Timing Simulation of Digital Integrated Circuits,"
Proceedings MIT Conference on Advanced Research in VLSI (Penfield ed), 93-99,
January 1984.
[5]
-
Lipton, Richard J.; North, Stephen C.; Sedgewick, Robert; Valdes, Jacobo; and
Vijayan, Gopalakrishnan, "ALI: a Procedural Language to Describe VLSI
Layouts," Proceedings 19th Design Automation Conference, 467-473, June 1982.
[8, 11]
-
Liu, Erwin S. K., "A Silicon Logic Module Compiler," Project Report,
University of Calgary Department of Computer Science, April 1984.
[4]
-
Locanthi, Bart, "Object Oriented Raster Displays," Proceedings 1st Caltech
Conference on VLSI (Seitz, ed), 215-225, January 1979.
[9]
-
Lopez, Alexander D. and Law, Hung-Fai S., "A Dense Gate Matrix Layout Method
for MOS VLSI," IEEE Transactions on Electron Devices, 27:8, 1671-1675,
August 1980.
[4]
-
Losleben, P., "Computer Aided Design for VLSI," Very Large Scale Integration
(VLSI) 5 (Barbe, ed), Springer-Verlag, Berlin, 89-127, 1980.
[1]
-
Losleben, Paul and Thompson, Kathryn, "Topological Analysis for VLSI Circuits,"
Proceedings 16th Design Automation Conference, 461-473, June 1979.
[5]
-
Luk, W. K., "A Greedy Switch-box Router," Carnegie-Mellon University
Department of Computer Science VLSI Document V158, May 1984.
[4]
-
Lyon, Richard F., "Simplified Design Rules for VLSI Layouts," Lambda,
2:1, 54-59, 1st Quarter 1981.
[5]
-
Lyon, Richard F., "The Optical Mouse, and an Architectural Methodology for
Smart Digital Sensors," Proceedings C-MU Conference on VLSI Systems and
Computations (Kung, Sproull, and Steele, eds), 1-19, October 1981.
[9]
-
Lyon, Richard F. and Schediwy, Richard R., "CMOS Static Memory with
a New Four-Transistor Memory Cell," Proceedings Stanford Conference on Advanced
Research in VLSI (Losleben, ed), 111-132, March 1987.
[11]
-
Malachi, Yonatan and Owicki, Susan S., "Temporal Specifications of Self-Timed
Systems," Proceedings C-MU Conference on VLSI Systems and Computations (Kung,
Sproull, and Steele, eds), Computer Science Press, 203-212, 1981.
[2]
-
Maley, F. Miller, "Compaction with Automatic Jog Introduction," Chappel Hill
Conference on VLSI (Fuchs, ed), 261-283, March 1985.
[4]
-
Mathews, Robert; Newkirk, John; and Eichenberger, Peter, "A Target
Language for Silicon Compilers," Proceedings 24th IEEE Computer Society
International Conference, 349-353, February 1982.
[8]
-
Mayo, Robert N., "Combining Graphics and Procedures in a VLSI Layout
Tool: The Tpack System," University of California at Berkeley Computer
Science Division technical report, January 1984.
[4, 8]
-
McCarthy, John; Abrahams, Paul W.; Edwards, Daniel J.; Hart, Timothy P.;
and Levin, Michael I., LISP 1.5 Programmer's Manual, MIT Press,
Cambridge, Massachusetts, 1962.
[7]
-
McCormick, Steven P., "EXCL: A Circuit Extractor for IC Designs," Proceedings
21st Design Automation Conference, 616-623, June 1984.
[5]
-
McCreight, E.M., "Efficient Algorithms for Enumerating Intersecting
Intervals and Rectangles," Xerox Palo Alto Research Center, CSL-80-9, 1980.
[3, 4]
-
McWilliams, Thomas M., "Verification of Timing Constraints on Large
Digital Systems," Proceedings 17th Design Automation Conference, 139-147,
June 1980.
[5]
-
Mead, C. and Conway, L., Introduction to VLSI Systems, Addison-Wesley,
Reading, Massachusetts, 1980.
[1, 3, 5, 6]
-
Metropolis, Nicholas; Rosenbluth, Arianna W.; Rosenbluth, Marshall N.;
Teller, Augusta H.; and Teller, Edward, "Equation of State Calculations by
Fast Computing Machines," Journal of Chemical Physics, 21:6, 1087-1092,
June 1953.
[4]
-
Miczo, Alexander, Digital Logic Testing and Simulation, Chapter 2:
"Combinational Logic Test," Harper and Row, New York, 1986.
[6]
-
Miller, George A., "The Magical Number Seven, Plus or Minus Two: Some Limits
on Our Capacity for Processing Information," Psychological Review, 63:2,
81-97, March 1956.
[1]
-
Mitchell, Tom M.; Steinberg, Louis I.; and Shulman, Jeffrey S., "A
Knowledge-Based Approach to Design," Proceedings IEEE Workshop on
Principles of Knowledge-Based Systems, 27-34, December 1984.
[4]
-
Moore, E. F., "Shortest Path Through a Maze," Harvard University Press,
Cambridge, Massachusetts, 285-292, 1959.
[4]
-
Mori, Hajimu, "Interactive Compaction Router for VLSI Layout," Proceedings 21st
Design Automation Conference, 137-143, June 1984.
[4]
-
MOSIS, MOSIS User's Manual, University of Southern California Information
Sciences Institute, 1986.
[7]
-
Mosteller, R. C., "REST-A Leaf Cell Design System," VLSI '81 (Gray, ed),
Academic Press, London, 163-172, August 1981.
[1, 4, 8]
-
Moszkowski, Ben, "A Temporal Logic for Multilevel Reasoning about Hardware,"
IEEE Computer, 10-19, February 1985.
[2]
-
Mukherjee, Amar, Introduction to nMOS and CMOS VLSI Systems Design,
Prentice-Hall, Englewood Cliffs, New Jersey, 1986.
[11]
-
Nagel, L. W., "Spice2: A Computer Program to Simulate Semiconductor
Circuits," University of California at Berkeley, ERL-M520, May 1975.
[5, 6, 11]
-
Nelson, Greg, "Juno, a constraint-based graphics system,"
Computer Graphics, 19:3, 235-243, July 1985.
[3, 8]
-
Newell, Martin E. and Fitzpatrick, Daniel T., "Exploiting Structure
in Integrated Circuit Design Analysis," Proceedings MIT Conference on Advanced
Research in VLSI (Penfield, ed), 84-92, January 1982.
[5, 9]
-
Newell, Martin E. and Sequin, Carlo H., "The Inside Story on Self-Intersecting
Polygons," Lambda, 1:2, 20-24, 2nd Quarter 1980.
[3, 9]
-
Newkirk, John and Mathews, Robert, The VLSI Designer's Library,
Addison-Wesley, Reading, Massachusetts, 1983.
[2]
-
Newman, William M. and Sproull, Robert F., Principles of Interactive
Computer Graphics, 2nd Edition, McGraw-Hill, New York, 1979.
[3, 9, 10]
-
Newton, Arthur Richard and Sangiovanni-Vincentelli, Alberto L.,
"Relaxation-Based Electrical Simulation," IEEE Transactions on
CAD, CAD-3:4, 308-331, October 1984.
[6]
-
Nogatch, John T. and Hedges, Tom, "Automated Design of CMOS Leaf Cells,"
VLSI Systems Design, VI:11, 66-78, November 1985.
[4]
-
Noll, A. Michael, "Man-Machine Tactile Communication," Society for
Information Display Journal, 1:2, 5-11, July/August 1972.
[9]
-
North, Stephen C., "Molding Clay: A Manual for the Clay Layout Language,"
Princeton University Department of Electrical Engineering and Computer
Science, VLSI Memo #3, July 1893.
[8]
-
Ousterhout, J. K., "Caesar: An Interactive Editor for VLSI Layouts,"
VLSI Design, II:4, 34-38, 1981.
[3, 10, 11]
-
Ousterhout, John K., "Crystal: A Timing Analyzer for nMOS VLSI Circuits,"
Proceedings 3rd Caltech Conference on VLSI (Bryant, ed), Computer
Science Press, 57-69, March 1983.
[5]
-
Ousterhout, John K., "Corner Stitching: A Data-Structuring Technique for VLSI
Layout Tools," IEEE Transactions on CAD, 3:1, 87-100, January 1984.
[3]
-
Patil, Suhas S., "An Asynchronous Logic Array," Project MAC tech memo TM-62,
Massachusetts Institute of Technology, May 1975.
[2]
-
Penfield, Paul Jr. and Rubenstein, Jorge, "Signal Delay in RC Tree
Networks," Proceedings 18th Design Automation Conference, 613-617, June 1981.
[5]
-
Pieper, Chris, "Stimulus Data Interchange Format," VLSI Systems Design,
Part I: VII:7, 76-81, July 1986; Part II: VII:8, 56-60, August 1986.
[7]
-
Piscatelli, R. N. and Tingleff, P., "A Solution To Closeness Checking
of Non-Orthogonal Printed Circuit Board Wiring," Proceedings 13th Design
Automation Conference, 172-178, June 1976.
[5]
-
Pope, Stephen; Rabaey, Jan; and Brodersen, Robert W., "Automated Design of
Signal Processors Using Macrocells," VLSI Signal Processing,
IEEE press, New York, 239-251, 1984.
[4]
-
Ramsay, Frank R., "Automation of Design for Uncommitted Logic Arrays,"
Proceedings 17th Design Automation Conference, 100-107, June 1980.
[4]
-
Reddy, D. R. and Rubin, Steven M., "Representation of Three-Dimensional Objects,"
Carnegie-Mellon University Department of Computer Science, Report CMU-CS-78-113,
April 1978.
[3]
-
Ritchie, D. M. and Thompson, K., "The UNIX Time-Sharing System,"
Bell Systems Technical Journal, 57:6, 1905-1929, 1978.
[10]
-
Rivest, Ronald L., "The 'PI' (Placement and Interconnect) System,"
Proceedings 19th Design Automation Conference, 475-481, June 1982.
[4]
-
Rivest, Ronald L. and Fiduccia, Charles M., "A 'Greedy' Channel Router,"
Proceedings 19th Design Automation Conference, 418-424, June 1982.
[4]
-
Rodriguez, Jorge E., A Graph Model for Parallel Computations, PhD
dissertation, Massachusetts Institute of Technology, Report MAC-TR-64,
September 1969.
[2]
-
Rogers, David F. and Adams, J. Alan, Mathematical Elements for Computer
Graphics, McGraw-Hill, New York, 1976.
[9]
-
Rosenberg, Jonathan B. and Weste, Neil H. E., "ABCD-A Better Circuit
Description," Microelectronics Center of North Carolina Technical
Report 4983-01, February 1983.
[8]
-
Roth, J.P., "Diagnosis of Automata Failures: A Calculus and a Method,"
IBM Journal of Research and Development, 10:4, 278-291, July 1966.
[6]
-
Rowson, James A., Understanding Hierarchical Design, PhD dissertation,
California Institute of Technology, TR 3710, April 1980.
[1]
-
Rubin, Steven M., "An Integrated Aid for Top-Down Electrical Design,"
VLSI '83 (Anceau and Aas, eds), North Holland, Amsterdam, 63-72,
August 1983.
[11]
-
Saito, Takao; Uehara, Takao; and Kawato, Nobuaki, "A CAD System For
Logic Design Based on Frames and Demons," Proceedings 18th Design Automation
Conference, 451-456, June 1981.
[8]
-
Saleh, Resve A.; Kleckner, James E.; and Newton, A. Richard, "Iterated Timing
Analysis in Splice1," ICCAD '83, 139-140, September 1983.
[6]
-
Sastry, S. and Klein, S., "PLATES: A Metric Free VLSI Layout Language,"
Proceedings MIT Conference on Advanced Research in VLSI (Penfield, ed),
165-169, January 1982.
[8]
-
Schediwy, Richard R., A CMOS Cell Architecture and Library, Masters thesis,
University of Calgary Department of Computer Science, 1987.
[2, 3]
-
Scheffer, Louis K., "A Methodology for Improved Verification of VLSI
Designs Without Loss of Area," Proceedings 2nd Caltech Conference on VLSI
(Seitz, ed), 299-309, January 1981.
[1, 5]
-
Schiele, W., "Design Rule Adaptation of Non-Orthogonal Layouts with Approximate
Scaling," VLSI '85, (Horbst, ed), 273-282, August 1985.
[4]
-
SCI, GENESIL System User's Manual, Silicon Compilers, Incorporated
publication 110016, November 1985.
[4]
-
Scott, Walter S. and Ousterhout, John K., "Plowing: Interactive Stretching and
Compaction in Magic," Proceedings 21st Design Automation Conference, 166-172,
June 1984.
[4]
-
Seattle Silicon, The Mentor Idea/Concorde User's Manual, Seattle Silicon
Technologies, Incorporated, publication UMC Beta 300 Rev 1, March 1986.
[4]
-
Sechen, Carl and Sangiovanni-Vincentelli, Alberto, "The TimberWolf Placement
and Routing Package," Proceedings Custom Integrated Circuit Conference,
522-527, May 1984.
[4]
-
Seiler, Larry, "A Hardware Assisted Design Rule Check Architecture,"
Proceedings 19th Design Automation Conference, 232-238, June 1982.
[5]
-
Seitz, Charles L., "System Timing," Introduction to VLSI
Systems (Mead and Conway), Addison-Wesley, Reading, Massachusetts, 1980.
[1]
-
Sequin, Carlo H., "Managing VLSI Complexity: An Outlook," Proceedings IEEE,
71:1, 149-166, January 1983.
[1]
-
Serbin, B. M., "QUAIL: An Interactive, Mixed-Mode, Multi-State Hierarchical Logic
Simulator," M.Sc. Thesis, Queen's University at Kingston, Department of Electrical
Engineering, 1987.
[11]
-
Shand, Mark A., "Hierarchical VLSI Artwork Analysis," VLSI '85,
(Horbst, ed), 419-428, August 1985.
[5]
-
Siewiorek, Daniel P.; Bell, C. Gordon; and Newell, Allen, Computer Structures:
Principles and Examples, McGraw-Hill, New York, 1982.
[2]
-
Simoudis, Evangelos and Fickas, Stephen, "The Application of Knowledge-Based
Design Techniques to Circuit Design," ICCAD '85, 213-215, November 1985.
[4]
-
Singh N. "MARS: A Multiple Abstraction Rule-Based Simulator," Stanford University
Heuristic Programming Project HPP-83-43, December 1983.
[11]
-
Soukup, Jiri, "Circuit Layout," Proceedings IEEE, 69:10, 1281-1304,
October 1981.
[4]
-
Southard, Jay R., "MacPitts: An Approach to Silicon Compilation,"
IEEE Computer, 74-82, December 1983.
[4]
-
Spickelmier, Rick L. and Newton, A. Richard, "Wombat: A New Netlist Comparison
Program," ICCAD '83, 170-171, September 1983.
[5]
-
Sproull, Robert F. and Sutherland, Ivan E., Asynchronous Systems II:
Logical Effort and Asynchronous Modules, to be published.
[3]
-
Stallman, Richard M., "The Extensible, Customizable Self-Documenting
Display Editor," Proceedings ACM SIGPLAN SIGOA Symposium on Text
Manipulation, Portland Oregon, 147-156, June 1981.
[10]
-
Stallman, R.M. and Sussman, G.J., "Forward Reasoning and Dependency
Directed Backtracking in a System for Computer-Aided Circuit Analysis,"
Artificial Intelligence, 9:2, 135-196, October 1977.
[8]
-
Stamos, James W., "A Large Object-Oriented Virtual Memory: Grouping Strategies,
Measurements, and Performance," Xerox PARC SCG-82-2, May 1982.
[3]
-
Steele, G. L. Jr., The Definition and Implementation of a Computer
Programming Language Based on Constraints, PhD dissertation, Massachusetts
Institute of Technology, August 1980.
[3, 8]
-
Supowitz, Kenneth J. and Slutz, Eric A., "Placement Algorithms for Custom VLSI,"
Proceedings 20th Design Automation Conference, 164-170, June 1983.
[4]
-
Sussman, Gerald Jay, "SLICES-At the Boundary between Analysis and
Synthesis," AI Memo 433, Massachusetts Institute of Technology, 1977.
[8]
-
Sussman, Gerald Jay and Steele, Guy Lewis, "CONSTRAINTS-A Language for
Expressing Almost-Hierarchical Descriptions," Artificial Intelligence,
14:1, 1-39, August 1980.
[3]
-
Sutherland, Ivan E., Sketchpad: A Man-Machine Graphical Communication
System, PhD dissertation, Massachusetts Institute of Technology, January
1963.
[3, 8]
-
Szabo, Kevin S. B.; Leask, James M.; and Elmasry, Mohamed I., "Symbolic
Layout for Bipolar and MOS VLSI," IEEE Transactions on CAD, CAD-6:2,
202-210, March, 1987.
[2]
-
Takashima, Makoto; Mitsuhashi, Takashi; Chiba, Toshiaki; and Yoshida, Kenji,
"Programs for Verifying Circuit Connectivity of MOS/LSI Mask Artwork,"
Proceedings 19th Design Automation Conference, 544-550, June 1982.
[5]
-
Teig, Steven; Smith, Randall L.; and Seaton, John, "Timing-Driven Layout of
Cell-Based ICs," VLSI Systems Design, VII:5, 63-73, May 1986.
[4]
-
Terman, Christopher J. "RSIM-A Logic-level Timing Simulator,"
Proceedings IEEE International Conference on Computer Design, 437-440,
October 1983.
[6]
-
Thornton, Robert W., "The Number Wheel: A Tablet Based Valuator for
Interactive Three-Dimensional Positioning," Computer Graphics, 13:2,
102-107, August 1979.
[10]
-
Tilbrook, David M., A Newspaper Pagination System, Masters Thesis,
University of Toronto Department of Computer Science, 1976.
[10]
-
Tompa, Martin, "An Optimal Solution to a Wire-Routing Problem," Proceedings
12th Annual ACM Symposium on Theory of Computing, 161-176, 1980.
[4]
-
Trimberger, Stephen, "Combining Graphics and A Layout Language in a Single
Interactive System," Proceedings 18th Design Automation Conference,
234-239, June 1981.
[8]
-
Trimberger, Stephen, "Automated Performance Optimization of Custom Integrated
Circuits," VLSI '83 (Anceau and Aas, eds), North Holland, Amsterdam,
99-108, August 1983.
[5]
-
Turing, A. M., "Computing Machinery and Intelligence," Mind, 59:236,
433-460, October 1950.
[8]
-
VanCleemput, W. M., "An Hierarchical Language for the Structural
Description of Digital Systems," Proceedings 14th Design Automation
Conference, 377-385, June 1977.
[2]
-
Varner, Denise, "Color Avionics," unpublished manuscript.
[10]
-
VLSI Design Staff, "A Perspective On CAE Workstations," VLSI Design, IV:4,
52-74, April 1985.
[7]
-
VLSI Systems Design Staff, "1986 Survey of Logic Simulators," VLSI
Systems Design, VII:2, 32-40, February 1986.
[6]
-
VTI, VLSI Design System, VLSI Technologies Inc., 1983.
[4]
-
Wang, Paul K.U., "Approaches to Hardware Acceleration of Circuit Simulation,"
Proceedings IEEE International Conference on Computer Design, 724-726,
October 1985.
[6]
-
Wardle, C. L.; Watson, C. R.; Wilson, C. A.; Mudge, J. C.; and Nelson, B. J.,
"A Declarative Design Approach for Combining Macrocells by Directed Placement
and Constructive Routing," Proceedings 21st Design Automation Conference,
594-601, June 1984.
[4]
-
Watanabe, Hiroyuki, IC Layout Generation and Compaction Using Mathematical
Optimization, PhD dissertation, University of Rochester Computer Science
Department, TR 128, 1984.
[4]
-
Weinberger, A., "Large Scale Integration of MOS Complex Logic: A Layout
Method," IEEE Journal of Solid State Circuits, 2:4, 182-190, 1967.
[4]
-
Weinreb, Daniel and Moon, David, "Flavors: Message Passing in the Lisp Machine,"
MIT Artificial Intelligence Lab Memo #602, November 1980.
[3]
-
Weste, Neil, "Virtual Grid Symbolic Layout," Proceedings 18th Design
Automation Conference, 225-233, June 1981.
[1, 2, 4, 8, 11]
-
Weste, Neil and Eshraghian, Kamran, Principles of CMOS VLSI Design,
Addison-Wesley, Reading, Massachusetts, 1985.
[2, 4]
-
Whelan, Daniel S., "A Rectangular Area Filling Display System Architecture,"
Computer Graphics, 16:3, 147-153, July 1982.
[9]
-
Whitney, Telle, "A Hierarchical Design-Rule Checking Algorithm,"
Lambda, 2:1, 40-43, 1st Quarter 1981.
[5]
-
Whitney, Telle, Hierarchical Composition of VLSI Circuits,
PhD dissertation, California Institute of Technology Computer Science, report
5189:TR:85, 1985.
[3]
-
Wilcox, C. R.; Dageforde, M. L.; and Jirak, G. A., Mainsail Language
Manual, Version 4.0, Xidak, 1979.
[8]
-
Williams, John D., "STICKS-A graphical compiler for high level LSI design,"
Proceedings AFIPS Conference 47, 289-295, June 1978.
[1, 2, 4, 8, 11]
-
Wilmore, James A., "Efficient Boolean Operations on IC Masks," Proceedings
18th Design Automation Conference, 571-579, June 1981.
[4, 5]
-
X3H3/83-25r3 Technical Committee, "Graphical Kernel System,"
Computer Graphics special issue, February 1984.
[9]
-
Wing, Omar; Huang, Shuo; and Wang, Rui, "Gate Matrix Layout," IEEE
Transactions on CAD, 4:3, 220-231, July 1985.
[4]
-
Zippel, Richard, "An Expert System for VLSI Design," Proceedings IEEE
International Symposium on Circuits and Systems, 191-193, May 1983.
[3, 8]