Micro8 - A Simple VHDL CPU

Micro8  - A very simple VHDL FPGA microprocessor

Micro8 started of as a minimal set 4 instruction computer By Tim Boscke designed to fit in a 32 Macrocell CPLD.
http://gforge.openchip.org/projects/mcpu/

I've added to it considerably and run it on the B3-Spartan2+ board using a Xilinx XC2S200.

Tim's computer had only ADD, NOR , STA and JCC instructions. It had a single carry bit which was set (?) by the JCC (Jump on Carry Clear) instruction. Most microprocessor instructions can be built up using these basic instructions.

In my Micro8 design I have an 8 bit accumulator and an 8 bit index register and four addressing modes, Immediate, Absolute, Indexed and PC Relative and I've extended the addressing range from 6 bits or 64 bytes to 11 bits or 2K bytes. The top five bits of the opcode byte determine the operation and addressing mode. the bottom 3 bits of the opcode form the high bits of the address argument. I've also added a Zero (Z) Flag and a Negative (N) flag and corresponding conditional branches that do not change the condition codes.

Micro8 uses 12% of an XC2S200, including the wishbone miniUART by Phillipe Carton.
Doug Hodson has a version of the Micro8 for the Xess XSA100 FPGA board on his RetroMicro web page.

21 May 2003 - Update
I've updated Micro8 to correct a number of problems. check out the Micro8 page for details

Micro8a - Adding a Stack

In my Micro8A I have added a 7 bit stack pointer at $0FF that works down to $080. I've added subroutine calls, Push and Pull registers
and interrupts as well as some inherent single byte instructions to operate on the accumulator and index register.

Micro8b - Extending the Index Register (Proposed Design)

Micro8b is a proposed enhancement to make the Index register 11 bits rather than 8 bits.  That means the index register can index the full addressing range of the microprocessor. ADDX and NORX instructions have been replaced with LDX and CPX as these are more common operations performed by an index register. INX and DEX instructions also need to be included in the opcode map.

This project has not progressed because it almost developed into a MC6805 design.

Similar Projects

Vincent Crabtree from Loughborough University has also extended Tim Boscke's design:
http://staffi.lboro.ac.uk/~elvpc/fpga/soc.html