Steps for power analysis of the reference design(DIGCAM) using the provided 
synthesis scripts.

MODIFICATIONS: The following modification to the gate-level vhdl file is
needed in order for simulation to work.

Comment out the line that define UNSIGNED type.  This is not needed and will
result in errors.

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Synthesizing and simulating the DIG_CAM.

1. Synthesize the entire design using the DIG_CAM_syn.scr.

2. Modify the gate-level VHDL output as described above.

3. Run the simulation by running sim.scr from the command prompt.  This will
output a toggle file "dig_cam_vss_toggle_count".

4. Convert the toggle file using the following command.

	sim2dp -vss dig_cam_vss_toggle_count > dig_cam_sa.scr

	NOTE: sim2dp is a script provided within the synopsys package.

5. Then run the "power.scr" file from within dc_shell to provide the 
power analysis results. The followign command should be used:

	include power.scr