Ports

Ports provide a means for a module to communicate through input and output. Let us go back to the E-type flip flop example given in the previous section. The input/ ouput of the D-type relative to the E-type is shown below.

module d_ff(q, d, reset, clock);
module e_ff(q, d, enable, reset, clock);
module Stimulus;

Port Lists

The I/O for the D-type is generated by the E-type, the I/O for the E-type is generated by the top level module in this case the stimulus. The stimulus module has no I/O so does not need a port list.

Every port in the port list must be declared as input, output or inout, in the module. All ports declared as one of the above is assumed to be a wire by default, to declare it otherwise it is neccessary to declare it again. For example in the D-type flip flop we want the ouput to hold on to its value until the next clock edge so it has to be a register.

        module d_ff(q, d, reset, clock);
             output q;              // all ports must be declared
             input d, reset, clock; // as input or output
             reg q;  // the ports can be declared again as required.

Note: by convention, the outputs of the module is always first in the port list. This convention is also used in the predefined modules in Verilog.