| Bus Ports
In EDIF 2 0 0, all the bus ports in LPM were flatten as single port due to lack of bus
support in EDIF specification. But in EDIF 3 0 0, the bus construct is well defined
therefore all the bus ports in LPM cell are maintain as bus in its' cell declaration. .
For example with a two-bit output bus in LPM_FF (i.e. LPM_Width = 2), the port name for
the Q output pin is declared as:
EDIF 3 0 0 example:
(port Q0 (outputPort)
(nameInformation
(primaryName "Q0"
(nameStructure
(complexName "Q"
(nameDimension
(nameDimensionStructure 0)))))))
(port Q1 (outputPort)
(nameInformation
(primaryName "Q1"
(nameStructure
(complexName "Q"
(nameDimension
(nameDimensionStructure 1)))))))
(portBundle Q
(portList
(portRef Q1)
(portRef Q0)
(nameInformation
(primaryName "Q[1:0]"
(nameStructure
(complexName "Q"
(nameDimension
(nameDimensionStructure
(sequence 1 0)))))))))
Both input numbers and bus numbers start with zero as the least significant bit. And
the rename construct that used to hold original name in EDIF 2 0 0 is replaced by
the primaryName in the nameInformation construct.
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