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These examples of syntisable designs are available on VHDL.ORG 
proposed by NAVABI (navabi@ece.neu.edu) 
(RTL models are available only here) 
ORIGINAL ---- Behevioral definitions 
RTL      ---- RTL synthesis (Y.HERVE ERM/PHASE with EXEMPLAR/CORE) 
HARDWARE ---- structural (pAsic targetted) 
TESTING/LIST  listfil output of tests (V-SYSTEM/MODELTECH ?) 
TESTING/TEST  testbenchs  
SIM_LIB/PAsic20.VHD   gate models for structural simulation 
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Current directory is /public/vhdl/models/MSI/synth_models
 
  Up to higher level directory 
  Hardware/ -- structural (pAsic targetted)
  Original/ -- Behevioral definitions
  RTL/      -- RTL synthesis (Y.HERVE ERM/PHASE with EXEMPLAR/CORE)
  Sim_Lib/  -- gate models for structural simulation
  Testing/
  read.me