VHDL Modelling Guidelines (Format: PostScript)
The European Space Agency has decided that VHDL shall be used in contracts that include design of electronics for spacecraft.
VHDL Modelling Guidelines (Format: PostScript)
The purpose of these guidelines is to ensure a good coding standard for VHDL, w.r.t. to readability, portability and a high level of verification. There are separate sections dealing with specific requirements for VHDL models for component simulation, board-level simulation, system-level simulation and testbenches. Author: Peter Sinander. Also available in Adobe PDF format.
The VHDL Standard Report (Format: PostScript)An overview of the current (May 1994) status of the VHDL standard and associated activities within the IEEE, EIA, and ESPRIT projects. An extensive summary of VHDL repositories is included, together with a list of European VHDL tools. Also available in Adobe PDF format.
The Usage of VHDL in the European Space Agency (Format: PostScript)Outlines how VHDL is used in European Space Agency activities, in particular focusing on the need for modelling guidelines and an approach to use VHDL for board-level simulation. Author: Peter Sinander.
Accelerated Verification of Digital Devices Using VHDL (Format: Adobe PDF)
This paper presents two aspects for improving the verification of microprocessors; program-less verification, and methods for handling large differences in abstraction level between a reference model and the actual design. Program-less verification is a type of pseudo random verification where the notion of a software program executing on the microprocessor has been abandoned. Author: Sandi Habinc and Peter Sinander (ESA/ESTEC TOS-ESM).
Using VHDL for Board-Level Simulation (Format: PostScript)Prototyping is a necessity for successful development of printed circuit boards built with complex components such as microprocessors, ASICs and ASSPs. In this paper an approach to prototyping are presented based on VHDL models for board-level simulation written for high functional accuracy and simulation performance. Authors: Sandi Habinc and Peter Sinander. Also available in Adobe PDF format.
VHDL Models for Board-level Simulation (Format: PostScript)This document provides recommendations for development and usage of VHDL models intended for Board-level simulation. The purpose of these recommendations is to define modelling criteria that will produce models that are highly accurate in both functionality and timing, and that will provide sufficient simulation performance to facilitate long simulation runs. Author: Sandi Habinc. Also available in Adobe PDF format.
VHDL Models for Board-level Simulation Source Code ExamplesSource code examples to the document above.
ESA.Simulation
In this package the enumerated type SimConditionType, to be used to select Worst, Typical or Best Case values for timing parameters in VHDL models for board-level simulation.
Information about VITAL (VHDL Initiative Toward ASIC Libraries)A compilation of information concerning VITAL (documents and VHDL code).
Program-to-MIF (FrameMaker Interchange Format) translator: prog2mifPretty printer for several languages, converts an ASCII source file to a FrameMaker MIF file. Italicizes comments, boldens key words. Does NOT reformat the text for indentation. Supports ADA, C, C++, LISP, OBJC, M, PERL, PROTEL, SH, Verilog and VHDL. Requires the perl utility to run (available from e.g. ftp.uu.net in /languages/perl).
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