Objectives:

The objective of this lab is to introduce the student to dynamic storage elements. This lab is actually the first part of the VLSI Class project.

Introduction

The spice models you are to use for this lab can be found in:

 ~reese/EE4253/project/scn08hp/nominal.bsim

Dynamic D Flip-Flops

You will be given a handout in lab that contains the schematics of three dynamic D Flip-Flops:

• Positive edge-triggered D FF (a)
• Negative edge-triggered D FF (b)
• Positive edge-triggered D FF using split output latches (c)

Look at the project assignments page ( here ) to see which D FF you are assigned. For those of you assigned either DFF (a) or DFF (b) you need to make a slight change for better operation:

• If you have DFF (a), in the second column of transistors (2nd stage), exchange the positions of the bottom NMOS transistor (gate tied to 'phi') with the NMOS transistor above it (gated by signal 'X').
• If you have DFF (b), in the second column of transistors (2nd stage), exchange the positions of the top PMOS transistor (gated tie to 'phi') with the PMOS transistor below it (gate tied to the output of the previous stage).

What You Must Do For Next Week

• Simulate your D FF in Hspice and verify its operation (transistor sizing is up to you, this schematic will eventually be implemented in the scn08hp process). Do this by connecting the FF in a divide-by-two configuration (the 'Q_not' output is tied back to the D input, the Q output will now be the CK frequency divided by 2).
• Modify the schematic to add a LOW TRUE reset pin called 'R'. This should be an ASYNCHRONOUS reset. Test your new implementation with the following test cases:
  1. Initialize the FF to a '1' (D = '1', R = '1', apply one clock period), then set D = 0, pulse 'R' low (bring to '0' then back to '1') when clock = HIGH, observe Q going low BEFORE the clock goes back LOW (set the length of the clock period to whatever you want). You should observe Q remaining low for ALL remaining clocks (clock at least a couple of times).
  2. Same as previous simulation apply 'R' when CK = LOW.
  3. Initialize the FF to a '1' (D = '1', 'R' = '1', apply one clock period), then set D = 1, pulse 'R' low (bring to '0' then back to '1') when clock = LOW, observe Q going low BEFORE the clock goes back HIGH (set the length of the clock period to whatever you want). You should observe Q remaining low until the NEXT active clock edge, at which point Q should go back high (clock at least a couple of times).
  4. Same as previous simulation except apply 'R' when CK = HIGH.
  This should cover all asynchronous reset cases. Your asynchronous reset SHOULD NOT dissipate static power. Create a plot of supply current; given a signficantly long enough settling period the supply current should always return to near 0. Show that this is the case for your circuit in all of the simulations discussed above when 'R' is asserted.

HSPICE Tips

In all tests, you will need to add a capacitor on the output node; use a 15 FF capacitor. Use 50ps rise/fall times for all signals. Use Vdd = 5 volts. Use a long clock period to allow internal node voltages to settle (20 ns should be plenty, you can use a longer period if desired). In this lab, we are only worried about functional operation.

When adding the low true reset, you will need to carefully track the states of internal node voltages; you may have to reset more than one internal node voltage. This means adding more than pullup/pulldown transistor. The node voltages you need to be concerned with are those between each stage (between 1st/2nd stages, between 2nd/3rd stages, and the 'Q_not' node voltage). Adding enough transistors to reset each of these voltages to 0 will certainly get the job done but may be overkill; each transistor you add will be another transistor that you will have to eventually include in your layout so it is advantageous to add as few transistors as possible.

Misc

• You do not have to do any layout for this assignment (this will be assigned in a later lab).
• You must create an LED schematic for your FF that has the asynchronous reset added. This is for documentation purposes; you can create your HSPICE model in any manner you want.