Lab7: Hierarchical Layout

EE 4253/6253 VLSI Laboratory
Lab7: Hierarchical Layout

Objectives:

To gain experience with hierarchical layout in Led, transistor level simulation with Lsim, and layout versus schematic checking. Make sure you read through this entire handout before class.

Set Up

Make a directory for your work. Change to this directory and execute the command:


 ln -s /ecad/local/tech/rel/gdt/scn08hp.dir/Ledrc

This creates a symbolic link to the Led initialization file for the scn08hp technology. In this technology, lambda = 0.4U.

Copy all files from:


 ~reese/EE4253/lab7

to this directory.

Hierarchical Layout

One of the files which you copied is called 'fa.S'. This is the schematic for 1-bit full adder using standard cells from the MSU SCMOS Standard cell library. You are to manually create a standard cell type layout for this schematic. A standard cell layout has rows of abutting standard cells with routing channels between rows. If all of the routing for connecting the cells can be run over the top of the layout, then the routing channels might not be present.

Look at the 'bj_struct.L' file which you copied over. This is an example of a standard cell layout. Note how the routing is done in MET2/MET3 (MET2 vertical, MET3 horizontal). Use the 'p' command (plot control) and set the plot depth to '1'. Then use the 'S' command (Plot Attributes) and set the 'instance term plot' to 'off'. This will let you see the routing in more detail. Also take note of the vertical power cells that are added on each side of the layout.

The 'bj_struct.L' file is known as a 'hierarchical' layout because it contains multiple layout hierarchies. The individual cells are 'instances' which are contained inside the 'bj_struct' cell; routing is also defined in the 'bj_struct' cell. To edit the layout of one of the cell instances you would have to push into this cell (push down in the heirarchy) to perform the editing. Any editing done inside of a cell would affect all cell instances of this type. This lab will require that you create a hierarchical layout similar to the 'bj_struct' cell. Read this document to find out more details about hierarchical layout.

The 'fa.S' schematic has 7 standard cells. You are to create a layout which has two rows of cells, and you are to use MET2 and MET3 routes to connect the cells.

To get an idea of the size of each cell, bring up Led in the 'scn08hp' technology. In 'window 1', load the L file 'lib.L'. This file contains cell layout definitions for each of the cells from the SCMOS library which are used by the 'fa.S' schematic.
In the second window, create a new layout cell called 'fa'. Place down instances of the cells needed by the full adder circuit in the 'fa' cell. For now, don't worry about where to put them, just place them anywhere. You can use the command 'Add -> Add Instance of cell (b)' to do this.
Now that you have an idea of the relative sizes of the cells, arrange the cells into two rows, where each cell abuts with its neighbor. In placing the cells, think about how you are going to connect the cells. You can only use MET2/MET3 for the routing. You should try to follow a general scheme where MET2 runs vertically, and MET3 runs horizontally. Place the two rows as close a possible to each other.
- The easiest way to abut two cells is to select one of the Vdd nodes of a cell, then use the 'w' command to move the cell. While you are moving the cell, drag a rectangle around the the Vdd terminal of the target cell you want this cell to abut with (select the target terminal just like you select the end-point for a wire). This will cause the two cells to abut, and there will now be a wire between the two terminals.
- When you are adding your routing, be careful of the 'muxf201' cell. It uses some MET2 internal to the cell; make sure your external MET2 routing does not short the internal cell routing.
You should be able place the two rows very close together and run most of the routes over the top of the cell. Use the 'p' command to change the plot depth to '1' when you just want to look at your routing.
Bring the schematic terminals ('a','b','ci', 'sum', 'co') to the top and bottom of the layout (bottom and top rows) and connect them to M1M2 contacts. Be sure to connect terminals of the proper type (IN,OUT) to these contacts and label them.
For Vdd/GND connections, add an instance of cell 'vert_pwr32' to the END of each row at the LEFT side (for this exercise, it is not necessary to add them to both sides). Make sure these cells are connected to the Vdd/Gnd rails of the row, then connect the Vdd/GND MET2 runs of the two 'vert_pwr32' cells together. This will connect Vdd/Gnd for ALL cells. Add terminals of type Vdd and GND to the instance terminals of one of the 'vert_pwr32' cells and label them as VDD0, GND0.
When you save your file, do a 'Write Cells and Leaves' (ctrl-w). This will write out the layout for your routing in addition to the layout for each of the cells.
Be sure that your layout passes the external DRC. The cells from the MSU SCMOS library already contain some '8.5' errors relating to poly contact to via spacing; you can ignore these errors. These are the only DRC errors that you should have in your layout.

Verification via LSIM simulation

One way to verify that your layout is correct would be to extract HSPICE and simulate it. For large layouts, HSPICE can be very slow. Often, all we want is a quick transistor level simulation just to check functionality. The Mentor LSIM simulator gives us this capability.

To extract a transistor level netlist that can be simulated in Lsim, do:


  mcExtGdt lsim fa.L

This will create a file called 'fa.N'. Take a look at the contents of this file; it is a transistor level netlist of your layout. You will need to edit this file inside of a texteditor and change the terminal types to be the correct type (IN, OUT, VDD, or GND). The 'mcExtGdt' extracts all of the top level terminals as INOUT terminals and this will confuse the Lsim simulator.

One of the files you copied is called 'fa.i'. This is a command file for LSIM which checks the functionality of your full adder. Look at this file, it is not hard to understand. To simulate this netlist using the 'fa.N' netlist and the 'fa.i' command file do:

 Lsim -l /ecad/local/tech/rel/gdt fa.N

The waveforms in the LSIM simulation should demonstrate the functionality of a full adder. The simulation also creates an output file called 'fa.lsim_out' which contains a log of the testvectors generated during the simulation. The correct values are contained in the file 'fa.lsim_out.golden'; do a 'diff' and see if your simulation results match the golden results.

Layout Versus Schematic Checking

For complex layouts, if a problem is found during simulation it is often difficult to determine the source of the problem. One common check which can be performed is layout versus schematic checking (LvS). This process extracts the transistor level schematic of the layout and compares it against the original transistor level schematic to see if they are equal. To run LvS on your design, do:


  ncGdt fa.L fa.S

Any mismatches between the layout and schematic will be written to a file called 'fa.ncErr'. This file can be difficult to interpret; look for the string 'NO MATE'. This will identify the node(s) in the layout that have no corresponding mates in the schematic, or vice-versa. It also gives the transistor nodes that are affected; however, the most useful information will the instance name of the cell that contains the affected transistor. If you have NO mismatches, then the 'fa.ncErr' file will be empty.

Requirements

Create the 'fa.L' layout that matches the 'fa.S'. Use the standard cell layout approach.
Verify that your 'fa.L' passes the external DRC except for 'Rule 8.5' errors.
Verify that the extracted Lsim netlist simulates correctly (there should be no differences between your testvector results and the golden results).
Verify that the layout versus schematic checker detects no mismatches.

You must demonstrate fulfillment of these requirements to the satisfaction of the TA.