EE 4253/6253 VLSI Laboratory
Lab6: Complex Gate Layout

Objectives:

To gain more experience with CMOS layout by creating the layout for a CMOS complex gate. The layout must follow the MSU standard cell layout template.

Set Up

Make a directory for your work. Change to this directory and execute the command: 


 ln -s /ecad/local/tech/rel/gdt/scn08hp.dir/Ledrc
This creates a symbolic link to the Led initialization file for the scn08hp technology. In this technology, lambda = 0.4U.

Complex Gate Layout Exercise

This lab involves creating the layout for the complex gate which you were assigned in Lab #2. You must do a stick layout of your gate on graph paper. Your stick layout must use an unbroken strip of diffusion for the NMOS and PMOS transistors. You must get your stick diagram checked by the TA before doing any actual layout in Led. Use a 4 lambda width for the NMOS transistors and an 8 lambda width for the PMOS transistors in your layout.

Your Led layout is to follow a layout template used at MSU for producing cells which are compatible with the Mentor Standard Cell place and route tool (we will use the Mentor Standard Cell place/route program in a later lab). The complete template definition is defined here (see Figure 2.1). Some of the more important template rules are:

  1. Cell height is 78 lambda.
  2. The cell width is a multiple of 8 lambda (there is no maximum). The cell width is determined by the outermost edges of the VDD/GND rails.
  3. Terminals must be brought out to M1M2 contacts inside of the cell. Valid X locations for terminals are on an 8 lambda grid, where the first posistion starts at 4 (locations are 4, 12, 20, 28, etc.). Terminals should also have a TERMPLACE property attached with the value 'TOP;BOTTOM'. This allows the Standard Cell place route tool to access this terminal from either the top or bottom of the cell.
  4. The power rails are in MET1 and are 10 lambda wide.
  5. Active, poly, or metal layers must be at least 2 lambda from the left and right edges of the cell.
  6. Use of MET2 for routing inside of the cell must be kept to an absolute minimum (it is preferable that you do not use it at all). If you do use MET2, then it should ONLY be in the vertical direction and on the same grid as the terminals.
A sample template in the scn08hp technology can be found in '~reese/EE4253/lab6/template.L'. The layout for a two input NAND gate (nanf201.L) can also be found in the same directory.

Requirements

  1. The perl script '~reese/bin/check_stdcell.perl' will check your standard cell layout for basic compilance with the standard cell template policy. To run the script, do: 
      ~reese/bin/check_stdcell.perl 0.4 myfile.L
    If you receive no printed messages containing the string 'ERROR', then your cell has passed.
  2. Your cell must pass the external DRC with no errors.
  3. You must extract the HSPICE netlist for your gate and verify its operation using the 'cgate_dc.sp' file used in the Lab #2 assignment. Extract the hspice file for this circuit using the 'mcGdtExt' program.