Constraint Driven Digital Design
What are we trying to accomplish?
Accomplishing objectives while meeting constraints is the key to any design process.
Power, delay and area are the constraints in cell-based submicron design.
The object of this research is provide a general approach to constraint driven digital design
for cell-based implementations which provides compatibility with CAD tools from multiple
sources, efficiency in design time and costs for prototyping, dense
layouts for cost effective fabrication, and flexibility to configure
to the specific requirements. Essential ingredients in meeting this
objective are:
- layout generation with parameterized device sizes
and parameterized design rules
- macromodeling of the timing for
parameterizable leaf cells
- CAD tools for determining the
appropriate device sizes (based on design constraints)
- interface
utilities to the synthesis tools
- interface utilities to the CAD
physical design tools
- the overall design methodology.
What is our approach?
There are several keys to the puzzle. One is the effective use of
third metal interconnect to improve layout density; it is also vital
that this third metal interconnect be used in a generic manner which
proves adaptable to CAD tools from multiple vendors. The second is
the ability for automatic and parameterizable generation of leaf
cells from a netlist or equivalent. The third key relates to device
sizing given the constraints of the design. The fourth key
relates to the efficient integration of the above technologies into
the top down design process, particularly using synthesis.
Our approach for generating the solutions to these keys is to combine
capabilities already available in commercial CAD systems with innovative
methodologies and locally-generated point tools to produce a system-level
solution. The solutions we are borrowing from commercially-available CAD systems
include logic and high synthesis capability; leaf-cell generation, and an
overall CAD framework. To this we are adding generator library development;
improved macromodeling of delay, power, and area based on transistor sizes;
improved path-delay analysis and optimization; and design-specific library
optimization.
Recent Results
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Completed the GCMOS standard cell library. The GCMOS library is a small
standard cell library, MOSIS-compatible, which is based on generators.
Cells can be generated based on drive strengths or cell heights, or a combination.
This library is being used to experiment
with cell library generation which is optimized on a DESIGN-BY-DESIGN basis.
Current commercial practice is to generate a fixed-height library which is optimized for area,
and another one which is optimized for speed; and then let users design to one
of the two libraries. Our approach to generate a new cell library optimized for
a particular design's constraints. In fact, several libraries might be generated for a
particular design, with different sub-blocks of the design using different libraries.
We anticipate making the library publicly available Spring '97. We are currently using
a pipelined,32-bit processor as the driver application for the library and point tools.
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A delay macromodel has been developed for use
with the GCMOS library. This macromodel provides delay prediction given desired
drive strength, input slew rate, and output capacitive load. This
macromodel is used to generate the Synopsys-compatible logic
synthesis library files required to perform design optimization
which targets the GCMOS library.
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Released an update to the MSU SCMOS fixed cell library. This release has
significantly streamlined tech files for MOSIS processes and also incorporates
several methodology improvements available within the Mentor/SCS tool suite.
The improvements include flattened mask-level
design rule checking, layout-versus-schematic checking, HSPICE/LSIM transistor extraction
from mask information, a padframe generator, and a pad library.
Additional Documentation
Library/Software Distributions