EE295 - ASIC Design Using VHDL

Simulation Lab

Much of the time spent designing an ASIC is spent in simulation - verifiying - that the design specification is accurate. How you code your VHDL design can effect how quickly it simulates and how effectively it synthesizes. Ultimately, these effect your product time-to market, cost and competetiveness.

In this exercise you must describe a popular logic function in several styles - using several architectures. You must then quantitatively compare the effective throughput of these architecutes and rationalize the results.

Counter Functions are a common ASIC Building block and there are many different ways of implimenting a counter in an ASIC design environment. Perhaps the foundry has selected some counter implimentations and provided them to you as components in a package. Perhaps your design team has invested significant engineering resource in designing this particular function at the transistor level for optimal results.

In this exercise we examine a simple common logic function - the counter. You will code a counter entity and - at a minimum - 3 architectures implimenting a counter function. Using a Testbench - you will exercise the various counter implimentations and comment on how much time each implimentation took to execute.

Getting Set Up

1. Assuming you have a favorite text editor all lined up
2. Log into a workstation and from your home directory..
3. mkdir cs295 - You have created a directory to store all of your class related work.
4. cd cs295
5. execute ~jswift/mti.sh in the korn shell - or -

   #!bin/ksh
   echo preparing MTI environment
   export VSYSTEM=~/cs295/vsystem.ini
   export WORK=~/cs295/work
   export MODEL_TECH=/usr/local/tools2/edatools/modeltech_v4.4a
   export PATH=$PATH:$MODEL_TECH/rs6000
   

6. copy /usr/local/tools2/modeltech_v4.4a/vsystem.ini ./
7. mkdir lab1 --to store your vhdl for this first lab
8. vlib work -- creates special directory named work
9. vmap work work -- Links VHDL Library work to special directory named work
10. vcom - Compile VHDL into work.
11. Additional Information on MTI's V-System Simulator

The Counter

A counter 'counts' electrical pulses or clocks and stores that count in a register. From a 'dataflow' point of view one impliments a counter by registering a value and incrimenting - or adding '1' - to the previous value in the register and updating the register.

1. The Behavioral Counter

   Prepare a file ~/cs295/lab1/counter.vhd containing the following design objects:

   • The Entity

     From the diagram presented above describe an entity for a counter. Assume that all ports are type std_logic & std_logic_vector. Any names are ok.

   • The Sequential Architecture

     From the diagram presented above describe an architecure for a counter using a process and sequential language elements. Hint: an IEEE package called std_logic_arith defines a type unsigned for which a + operator is defined. A signal or variable of type unsigned can be used to effect an add operation and there is a conversion function for assigning it to a std_logic_vector port.

     eg. count <= conv_std_logic_vector( int_count, 12 );

   • Analyze these using vcom lab1/counter.vhd

2. The TestBench

   Prepare a testbench for the counter design either adding it to counter.vhd or in a new file called ctb.vhd. A testbench has no ports in the entity and declares/ instantiates the counter as a component for the purpose of verifying function.

   You will need to specify a configuration. We haven't discussed this in the lectures yet but skip ahead and learn how to code one.

   You will want to apply values to the inputs and observe the outputs. Analyze this design using vcom. For a good example of a testbench design see /usr/local/tools2/modeltech_v4.4a/examples/adder.vhd & testadder.vhd. Your testbench should cycle the counter through all 2**12 ( 4096 ) possible values. Make note of how long the simulation takes to run.

3. Use vsim to elaborate and run your testbench design

4. The Structural Architecture

   Prepare an architecture that impliments a counter out of components. Return to /usr/local/tools2/modeltech_v4.4a/examples/adder.vhd & gates.vhd. You may compile these into library work and use the adder entity to impliment this. Note - Do NOT use AdderN but examine it for a suggested solution. Use a Guarded Block to impliment the register operation.

   Create a Configuration to Select This Architecture and Rerun vsim Selecting this Configuration. Make note of how long the simulation takes to run.

5. The Dataflow Architecture

   Prepare an architecture that uses concurrent expressions to impliment the counter function.

   Create a Configuration to Select This Architecture and Rerun vsim Selecting this Configuration. Make note of how long the simulation takes to run.

6. Submit a report with all of your VHDL and a summary of execution times vs architectural styles. Discuss your results.