Simulating the Placed and Routed Design

These instructions assume that you have successfully run XMAKE on your design to get a placed and routed LCA file.

1. Run XDM->XSIMMAKE. Choose your design's LCA file as input, and use the flow Viewlogic_Fpga_Timing. This starts the following sequence of events, with results logged in the file xsimmake.out:

   WHAT XSIMMAKE DOES

   1. XDELAY measures path delays and writes the information into the LCA file.
   2. LCA2XNF converts the LCA file into a Xilinx XNF file.
   3. XNFBA back-annotates the new XNF file with labels from the pre-routing XFF file.
   4. XNF2WIR converts the XNF file to Viewlogic wirelist format.
   5. VSM extracts a netlist from the wirelist file for ViewSim, writing it to sdesign.vsm.

2. If the steps to this point have been successful, you can run ViewSim on the s*.vsm file. If back-annotation of labels was successful, you should be able to simulate using the same .cmd file you used in preliminary VHDL simulations. You should pay particular attention to how long after each clock the slowest outputs take to settle to a value. This will provide you with a good approximation to your circuit's operating frequency.