REVIEW
















REVIEW - TIMING




1. Objects and Classes :





  • Signals for hardware carriers
  • Variables as temporary carriers
  • Constants for fixed parameters
  • A signal is an object whose class is signal










REVIEW - TIMING




2. Signals and Variables :





  • Signal assignments have a time component
  • x_sig <= value AFTER 6 NS;










REVIEW - TIMING




3. Concurrent and Sequential Assignments :





  • val2 and val3 are sequentially placed on z_sig
  • Assignment of a_sig to y_sig is done:
  • in the concurrent body, when event occurs on a_sig
  • in the sequential body, when program flow reaches it










REVIEW - TIMING




4. Events, Transactions and Delta_delays :




  • A signal assignment causes the placement of a transactionon the driver of the left hand side signal
    Transaction Representation: (value , time)

  • A transaction has a value and a time component
  • The time component of a transaction continuously decreases
  • Transaction is expired when its time component reaches 0
  • A signal receives value when a transaction on its driver expires







Events, Transactions and Delta_delays: 


    
ARCHITECTURE concurrent OF timing_demo IS    
      SIGNAL a, b, c : BIT := '0';
BEGIN
      a <= '1';
      b <= NOT a;
      c <= NOT b;
END concurrent;





  • Another delta example
  • Zero real time is spent from change on a until cstabilizes







Events, Transactions and Delta_delays 


    
x <= y;
y <= NOT x;



  • An interesting example
  • Assignments model zero delay inverter/buffer connection
  • Oscillation continues forever in zero real time


















REVIEW




Resolution Functions











REVIEW - RESOLUTION FUNCTIONS




1. Multiple Assignment : 





    
USE WORK.basic_utilities.ALL;
--  FROM PACKAGE USE: TYPE qit IS ('0', '1', 'Z', 'X');   
ENTITY y_circuit IS
    PORT (a, b, c, d : IN qit; z : OUT qit);
END y_circuit;
--
ARCHITECTURE smoke_generator OF y_circuit IS
    SIGNAL circuit_node : qit;
BEGIN
    circuit_node <= a;
    circuit_node <= b;
    circuit_node <= c;
    circuit_node <= d;
    z <= circuit_node;
END smoke_generator;


  • Normally several sources cannot drive a signal
  • Real circuits smoke







Multiple Assignments



  • Multiple drivers is possible only if a resolution exists
  • Example in hardware is "open collector"
  • Pull_up provides resolution
  • A convenient symbol is shown







Multiple Assignments


    
--  FROM basic_utilities USE qit, qit_vector, "AND" 
FUNCTION anding ( drivers : qit_vector) RETURN qit IS    
  VARIABLE accumulate : qit := '1';
BEGIN
  FOR i IN drivers'RANGE LOOP
    accumulate := accumulate AND drivers(i);
  END LOOP;
  RETURN accumulate;
END anding;




  • VHDL uses resolution functions
  • Resolving multiple values to a single value
  • Function parameter must be vector of its return type
  • All drivers are checked







Multiple Assignments


    
USE WORK.basic_utilities.ALL;
--  FROM PACKAGE USE: qit
ARCHITECTURE wired_and OF y_circuit IS
    FUNCTION anding ( drivers : qit_vector) RETURN qit IS   
      VARIABLE accumulate : qit := '1';
    BEGIN
      FOR i IN drivers'RANGE LOOP
        accumulate := accumulate AND drivers(i);
      END LOOP;
      RETURN accumulate;
    END anding;
    SIGNAL circuit_node : anding qit;
BEGIN
    circuit_node <= a;
    circuit_node <= b;
    circuit_node <= c;
    circuit_node <= d;
    z <= circuit_node;
END wired_and;




  • Specify anding for the resolution on circuit_node
  • Type of circuit_node is a subtype of qit
  • ANDing simultaneously receives all drivers










REVIEW - RESOLUTION FUNCTIONS




2. Wire Resolution : 




  FUNCTION wire (a, b : qit) RETURN qit IS
    CONSTANT qit_wire_table : qit_2d := (
                             ('0','X','0','X'),
                             ('X','1','1','X'),
                             ('0','1','Z','X'),
                             ('X','X','X','X'));
  BEGIN
    RETURN qit_wire_table (a, b);
  END wire;






  FUNCTION wiring ( drivers : qit_vector) RETURN qit IS
    VARIABLE accumulate : qit := 'Z';  -- wire value with no drivers  
  BEGIN
    FOR i IN drivers'RANGE LOOP
      accumulate := wire (accumulate, drivers(i));
    END LOOP;
    RETURN accumulate;
  END wiring;

  FUNCTION wiring ( drivers : qit_vector) RETURN qit;
  SUBTYPE wired_qit IS wiring qit;
  TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit;


  • A complete resolution for wiring










REVIEW - RESOLUTION FUNCTIONS




3. Three State Modeling : 





    
bi : BLOCK (si = '1' OR si = 'z')
BEGIN
    t <= GUARDED ii;
END BLOCK;
      . . .


  • A mux made of pass transistors
  • Each ii connects to t if si is '1'
  • ii is disconnected from t if si is '0'







Three State Modeling 


    
USE WORK.basic_utilities.ALL;
--  FROM PACKAGE USE: wired_qit
ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS  
  SIGNAL t : wiring qit BUS;
BEGIN
  b7: BLOCK (s7 = '1' OR s7 = 'Z') 
    BEGIN  t <= GUARDED i7; END BLOCK;
  b6: BLOCK (s6 = '1' OR s6 = 'Z') 
    BEGIN  t <= GUARDED i6; END BLOCK;
  b5: BLOCK (s5 = '1' OR s5 = 'Z') 
    BEGIN  t <= GUARDED i5; END BLOCK;
  b4: BLOCK (s4 = '1' OR s4 = 'Z') 
    BEGIN  t <= GUARDED i4; END BLOCK;
  b3: BLOCK (s3 = '1' OR s3 = 'Z') 
    BEGIN  t <= GUARDED i3; END BLOCK;
  b2: BLOCK (s2 = '1' OR s2 = 'Z') 
    BEGIN  t <= GUARDED i2; END BLOCK;
  b1: BLOCK (s1 = '1' OR s1 = 'Z') 
    BEGIN  t <= GUARDED i1; END BLOCK;
  b0: BLOCK (s0 = '1' OR s0 = 'Z') 
    BEGIN  t <= GUARDED i0; END BLOCK;
  z <= t;
END multiple_guarded_assignments;


  • Disconnection is realized by block statements
  • If all drivers are disconnected
Real hardware returns to 'Z'
Use BUS to implement this behavior
  • Default in wire is 'Z'
  • This default is used if wiring is called with null
  • Last disconnection causes call to wiring with Null










REVIEW - RESOLUTION FUNCTIONS




5. Signal Kind : 


    
USE WORK.basic_utilities.ALL;
--  FROM PACKAGE USE : qit, qit_vector, wired_qit
ENTITY mux_n_to_1 IS
  PORT (i, s : IN qit_vector; z : OUT wired_qit BUS);
END mux_n_to_1;
--
ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS 
BEGIN
  bi: FOR j IN i'RANGE GENERATE
    bj: BLOCK (s(j) = '1' OR s(j) = 'Z') 
    BEGIN
      z <= GUARDED i(j); 
    END BLOCK;
  END GENERATE;
END multiple_guarded_assignments;


  • A useful unconstrained multiplexer
  • Will know size when instantiated